Patents by Inventor Alexander C. Klaiber

Alexander C. Klaiber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9317284
    Abstract: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: April 19, 2016
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Alexander C. Klaiber
  • Publication number: 20160092217
    Abstract: In an embodiment, a processor may implement a vector instruction set including one or more compare break instructions. The compare break instruction may take a pair of operands which may be compared to determine loop termination conditions, and may output a predicate vector indicating which vector elements correspond to loop iterations that are executed and which vector elements correspond to loop iterations that are not executed. The predicate vector may serve as a predicate to vector instructions forming the body of the loop, correctly executing the specified number of iterations. The compare break instruction may be coded to check for a variety of conditions (e.g. equal, not equal, greater than, less than, etc.). In an embodiment, the compare break instruction may take a predicate operand as well, which may be combined with the predicate vector produced by the comparison operations to produce the output vector.
    Type: Application
    Filed: May 5, 2015
    Publication date: March 31, 2016
    Inventors: Jeffry E. Gonion, Charles E. Tucker, Alexander C. Klaiber
  • Publication number: 20160092398
    Abstract: In an embodiment, a processor may implement a vector instruction set including a conditional termination instruction (CTerm). The CTerm instruction may take two source operands and compare them according to a specified condition, updating flags as a result of the instruction. The flags may be used to affect predicate vector generation to control vectorized loop execution. In an embodiment, the vector instruction set may also include a conditional termination predicate instruction (CTPred). The CTPred instruction may take a pair of predicate vectors and a set of flags as operands, and may generate: a predicate vector to control parallel processing of vector elements, and a set of flags to control further loop processing. Either instruction may be used to efficiently manage vector loops in various embodiments, or the instructions may be used together.
    Type: Application
    Filed: May 5, 2015
    Publication date: March 31, 2016
    Inventors: Jeffry E. Gonion, Charles E. Tucker, Alexander C. Klaiber
  • Publication number: 20150089188
    Abstract: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: Apple Inc.
    Inventors: Jeffry E. Gonion, Alexander C. Klaiber
  • Patent number: 8607025
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: December 10, 2013
    Inventors: Alexander C. Klaiber, David Dunn
  • Publication number: 20120131307
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventors: Alexander C. Klaiber, David Dunn
  • Patent number: 8127098
    Abstract: In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing in a processor; determining that the write attempts to establish a first mode in the processor in which privilege level protection is disabled and paging is disabled; and causing the guest to execute in a second mode in which privilege level protection is disabled and paging is enabled instead of the first mode. A computer accessible medium comprising instruction implementing at least a portion of the method is also described.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 28, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alexander C. Klaiber, Kevin J. McGrath, Hongwen Gao
  • Patent number: 8117421
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: February 14, 2012
    Inventors: Alexander C. Klaiber, David Dunn
  • Patent number: 7962909
    Abstract: In one embodiment, a processor comprises an execution core configured to execute instructions including instructions comprising a guest and a circuit coupled to the execution core. The circuit is configured to monitor the execution core, and is programmable to limit an execution of the guest in the execution core to an execution interval. In another embodiment, a method comprises establishing an execution interval for a guest to be executed in a processor; and initiating execution of the guest in the processor. The processor includes a circuit configured to monitor execution of the guest to detect an end of the execution interval. A computer accessible medium storing instructions which, when executed, implement the method is also contemplated.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 14, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Alexander C. Klaiber
  • Patent number: 7937700
    Abstract: In one embodiment, a processor comprises a plurality of registers configured to store processor state and an execution core coupled to the registers. The execution core is configured, during a switch between processor execution of a guest and processor execution of a virtual machine manager (VMM) that controls the guest, to save only a portion of the processor state to a memory. In another embodiment, a method comprises switching from processor execution of a first one of a guest and a virtual machine manager (VMM) to processor execution of a second one of the guest and the VMM, wherein the VMM controls execution of the guest; and during the switching, the processor saving only a portion of a processor state to memory.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: May 3, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander C. Klaiber, Michael Shawn Greske, Hongwen Gao
  • Patent number: 7937536
    Abstract: Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: May 3, 2011
    Inventors: Alexander C. Klaiber, Guillermo J. Rozas, David Dunn
  • Patent number: 7917740
    Abstract: In one embodiment, a processor comprises an execution core configured to detect a freeze event responsive to an error indication, an ignore error indication, and an instruction in a guest. The instruction belongs to a predefined subset of instructions associated with the error indication and the ignore error indication. The execution core is configured to exit the guest in response to detecting the freeze event. In some embodiments, the error indication and the ignore indication may be stored in one or more registers in the processor. In some embodiments, the instruction is a floating point instruction, the error indication is a floating pointer error indication, and the ignore error indication is an ignore floating point error indication. In some embodiments, the error indication may correspond to an error signal output by the processor, and the ignore error indication may correspond to an ignore error signal input to the processor.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 29, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander C. Klaiber, Michael S. Greske
  • Publication number: 20100138615
    Abstract: Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 3, 2010
    Inventors: Alexander C. Klaiber, Guillermo J. Rozas, David Dunn
  • Publication number: 20100122013
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Inventors: Alexander C. Klaiber, David Dunn
  • Patent number: 7707341
    Abstract: In one embodiment, a method is contemplated. An interrupt is received in a processor from an interrupt controller. Responsive to receiving the interrupt, the interrupt is masked in the interrupt controller to permit another interrupt to be transmitted by the interrupt controller to the processor. The other interrupt has a lower priority than the previously-received interrupt in the interrupt controller.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: April 27, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander C. Klaiber, William Alexander Hughes
  • Patent number: 7676629
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: March 9, 2010
    Inventors: Alexander C. Klaiber, David Dunn
  • Patent number: 7636815
    Abstract: Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: December 22, 2009
    Inventors: Alexander C. Klaiber, Guillermo J. Rozas, David Dunn
  • Patent number: 7620779
    Abstract: Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 17, 2009
    Inventors: Alexander C. Klaiber, Guillermo J. Rozas, David A. Dunn
  • Patent number: 7418584
    Abstract: In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the intercept indication and further responsive to detecting the event, execution circuitry in the processor is configured to exit the guest. In another embodiment, a method comprises: detecting an event that would cause a processor to transition to a first mode, wherein first code is to be executed in the first mode; and causing the first code to be executed in a guest responsive to the detecting. In still another embodiment, a computer accessible medium comprising instructions which when executed in response to detecting the event, cause the first code to be executed in a guest.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 26, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander C. Klaiber, Geoffrey S. Strongin, Kevin J. McGrath
  • Patent number: 7209994
    Abstract: In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: April 24, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander C. Klaiber, Hongwen Gao