Patents by Inventor Alexander Carreira

Alexander Carreira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Visualizing hardware cost in high level modeling systems
    Patent number: 7913217
    Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: March 22, 2011
    Assignee: Xilinx, Inc.
    Inventors: Alexander Carreira, Alexander R. Vogenthaler
  • Correlation of data from design analysis tools with design blocks in a high-level modeling system
    Patent number: 7493578
    Abstract: Methods are provided for processing design information of an electronic circuit design. A single path or multiple paths that are produced by a first design tool are an input for the method. Each path includes an ordered set of element names of the electronic circuit design. Each element name of each path is pattern matched with the names of design blocks of the electronic circuit design produced by a second design tool. Data indicative of a path produced by the second design tool that includes the design blocks that are pattern matched to the ordered set of element names is the output of the method.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Roger B. Milne, Alexander R. Vogenthaler, Jeffrey D. Stroomer, Bradley L. Taylor, Alexander Carreira
  • Visualizing hardware cost in high level modeling systems
    Patent number: 7444610
    Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 28, 2008
    Assignee: Xilinx, Inc.
    Inventors: Alexander Carreira, Alexander R. Vogenthaler
  • Wireless dynamic boundary-scan topologies for field
    Patent number: 7383478
    Abstract: A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: June 3, 2008
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Alexander Carreira, L. James Hwang, Roger B. Milne, Shay Ping Seng, Nabeel Shirazi