Abstract: An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0?k?M, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.

Abstract: Provided are molecules and methods for detecting enzymatic activity of various lysosomal storage enzymes. The molecules may be used as internal standards that may be combined with substrates that have improved solubility.

Abstract: Methods are provided for detecting enzymatic activity of various lysosomal storage enzymes using substrates that include: a sugar moiety; a linker moiety allowing the conjugation of sugar moiety with the remaining structure of the substrate; and two or more fatty acid chains or derivatives thereof at least one of which is sufficiently structured to provide improved solubility in aqueous or organic solvent systems. Also provided are internal standards, and inhibitors for use in detecting or reducing enzymatic activity using the inventive substrates.

Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ?T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ?T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ?T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ?T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

Abstract: Methods are provided for detecting enzymatic activity of various lysosomal storage enzymes using substrates that include: a sugar moiety; a linker moiety allowing the conjugation of sugar moiety with the remaining structure of the substrate; and two or more fatty acid chains or derivatives thereof at least one of which is sufficiently structured to provide improved solubility in aqueous or organic solvent systems. Also provided are internal standards, and inhibitors for use in detecting or reducing enzymatic activity using the inventive substrates.

Abstract: Substrates are provided that include compounds suitable for detecting the activity of an enzyme such as a lysosomal storage enzyme where the substrates include: a sugar moiety; a linker moiety allowing the conjugation of sugar moiety with the remaining structure of the substrate; and two or more fatty acid chains or derivatives thereof at least one of which is sufficiently structured to provide improved solubility in aqueous or organic solvent systems. Also provided are methods for using substrates for detecting enzymatic activity using the inventive substrates.

Abstract: A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Abstract: A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.