Patents by Inventor Alexander Chu
Alexander Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10256248Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.Type: GrantFiled: June 7, 2016Date of Patent: April 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani, Hiroyuki Ogawa, Chun Ge, Daxin Mao, Yanli Zhang, Alexander Chu, Yan Li
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Patent number: 10249640Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.Type: GrantFiled: June 8, 2016Date of Patent: April 2, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Zhenyu Lu, Alexander Chu, Kensuke Yamaguchi, Hiroyuki Ogawa, Daxin Mao, Yan LI, Johann Alsmeier
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Patent number: 10115440Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: GrantFiled: June 16, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Publication number: 20180197586Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.Type: ApplicationFiled: June 16, 2017Publication date: July 12, 2018Applicant: SanDisk Technologies LLCInventors: Qui Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu, Yen-Lung Jason Li, Tai-Yuan Tseng, Jong Yuh
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Patent number: 9947682Abstract: A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.Type: GrantFiled: October 27, 2015Date of Patent: April 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Nima Mokhlesi, Alexander Chu
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Patent number: 9922716Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.Type: GrantFiled: February 22, 2017Date of Patent: March 20, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Chia-Lin Hsiung, Yanbin An, Alexander Chu, Fumiaki Toyama
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Publication number: 20170358593Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.Type: ApplicationFiled: June 8, 2016Publication date: December 14, 2017Inventors: Jixin YU, Zhenyu LU, Alexander CHU, Kensuke YAMAGUCHI, Hiroyuki OGAWA, Daxin MAO, Yan LI, Johann ALSMEIER
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Publication number: 20170352678Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Zhenyu LU, Jixin YU, Johann ALSMEIER, Fumiaki TOYAMA, Yuki MIZUTANI, Hiroyuki OGAWA, Chun GE, Daxin MAO, Yanli ZHANG, Alexander CHU, Yan LI
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Publication number: 20170309339Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.Type: ApplicationFiled: February 22, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Chia-Lin Hsiung, Yanbin An, Alexander Chu, Fumiaki Toyama
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Patent number: 9721671Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.Type: GrantFiled: September 10, 2015Date of Patent: August 1, 2017Assignee: SanDisk Technologies LLCInventors: Alexander Chu, Jong Hak Yuh, Kwang-Ho Kim, Yenlung Li, Farookh Moogat
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Publication number: 20170076812Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.Type: ApplicationFiled: September 10, 2015Publication date: March 16, 2017Applicant: SanDisk Technologies Inc.Inventors: Alexander Chu, Jong Hak Yuh, Kwang-Ho Kim, Yenlung Li, Farookh Moogat
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Publication number: 20160370970Abstract: A method, apparatus, and computer-readable medium for a user interface (UI) for a head-mountable display (HMD). The method includes generating three-dimensional content for display by the HMD. The method also includes identifying three-dimensional coordinates for UI elements of the UI that are associated with the three-dimensional content. The three-dimensional coordinates identified within an angular range for the UI that includes a viewable region of a user while wearing the HMD. Additionally, the method includes, in response to a user input, displaying the UI elements at the identified three-dimensional coordinates over the three-dimensional content. The method may further include, after displaying the UI elements, moving the display of the UI elements on the HMD in a direction corresponding to a movement direction of the HMD in response to detecting movement of the HMD corresponding to movement of a head of the user wearing the HMD.Type: ApplicationFiled: June 22, 2015Publication date: December 22, 2016Inventors: Alexander Chu, Sophie Kim
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Publication number: 20160141301Abstract: A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.Type: ApplicationFiled: October 27, 2015Publication date: May 19, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Nima Mokhlesi, Alexander Chu
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Publication number: 20140210703Abstract: An apparatus and method for unlocking in a portable electronic device via orientation sensing are provided. The device includes a display screen and at least one orientation sensor. The method includes displaying at least one moveable object on the display screen, sensing a change in an orientation of the device, moving the moveable object in accordance with the sensed change in orientation, and unlocking the device if the moveable object moves in accordance with a predetermined movement.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: SAMSUNG ELECTRONICS CO. LTD.Inventors: Venkataramana NARASIMHAN, Alexander CHU
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Patent number: 7974134Abstract: In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.Type: GrantFiled: November 13, 2009Date of Patent: July 5, 2011Assignee: SanDisk Technologies Inc.Inventors: Fanglin Zhang, Jong Park, Man Mui, Alexander Chu, Seungpil Lee
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Publication number: 20110116320Abstract: In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Inventors: Fanglin Zhang, Jong Park, Man Mui, Alexander Chu, Seungpil Lee
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Patent number: D760273Type: GrantFiled: January 2, 2015Date of Patent: June 28, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lam Nguyen, James Edward Van Den Heuvel, Alexander Chu
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Patent number: D761284Type: GrantFiled: January 2, 2015Date of Patent: July 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lam Nguyen, James Edward Van Den Heuvel, Alexander Chu