Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract: There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.

Abstract: A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one clocked state-holding element. The method simulates the performance of the element for different implementation conditions; measures the performance of the element for each condition, and determines the implementation of the forced gating function using the measured performances.

Abstract: There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Abstract: A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

Abstract: A latch is provided which includes: a transparent catch latch having a data input, a data output and a control node arranged to receive a catch signal; a transparent pass latch having a data input connected to the data output of the transparent catch latch at an internal storage node, a data output, and a control node arranged to receive a pass signal; and logic circuitry having an enable input and a clock input connected to provide a gated clock signal to provide one of said catch signal and said pass signal. In another aspect an integrated circuit is provided with input and output guard flops, each including a transparent catch latch and a transparent pass latch, and further including a logic gate with an enable input and a clock input connected to provide a gated clock signal to at least one of the transparent pass latch of the input guard-flop and transparent catch latch of the output guard flop.

Abstract: There is disclosed a method, and apparatus for implementing the method, for determining a gating function for the input to one of a plurality of clocked state holding elements, comprising the step of: for each element determining a first Boolean function corresponding to the variables forming an input to the element; determining a gating function for the plurality of elements; and for each element determining a second Boolean function which provides the same result as the first Boolean function when the gating function has a value 1.

Abstract: There is disclosed a method, and associated apparatus, for optimizing a gating expression for controlling the clock gating to a set of clocked state holding elements, said gating expression comprising at least one variable, the method comprising the step of maximizing the conjunctive form of said at least one variable.

Abstract: There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.

Abstract: There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Abstract: There is disclosed a method of determining a forced gating function for at least one of a plurality of clocked state-holding elements, which forced gating function compares the input and output of said at least one element, the method comprising: simulating the performance of the element for different implementation conditions; measuring the performance of the element for each condition, and determining the implementation of the forced gating function in dependence on said measured performances.

Abstract: A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

Abstract: A latch is provided which includes: a transparent catch latch having a data input, a data output and a control node arranged to receive a catch signal; a transparent pass latch having a data input connected to the data output of the transparent catch latch at an internal storage node, a data output, and a control node arranged to receive a pass signal; and logic circuitry having an enable input and a clock input connected to provide a gated clock signal to provide one of said catch signal and said pass signal.