Patents by Inventor Alexander D. Peleg

Alexander D. Peleg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5757432
    Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: May 26, 1998
    Assignee: Intel Corporation
    Inventors: Carole Dulong, Alexander D. Peleg, Larry M. Mennemeier
  • Patent number: 5742529
    Abstract: In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a method for determining the absolute difference of the corresponding data elements. The method comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: April 21, 1998
    Assignee: Intel Corporation
    Inventors: Larry M. Mennemeier, Alexander D. Peleg, Coby Gottlieb
  • Patent number: 5701508
    Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: December 23, 1997
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, Larry M. Mennemeier, Alexander D. Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrick Lin, Ramamohan R. Vakkalagadda