Patents by Inventor Alexander D. Petruncola

Alexander D. Petruncola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8171480
    Abstract: In a processing system which includes a physical processor that includes multiple logical processors, multiple domains are defined for multiple processes that can execute on the physical processor. Each of the processes is assigned to one of the domains. Processor utilization associated with the logical processors is measured, and each of the domains is allocated to a subset of the logical processors according to the processor utilization.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: May 1, 2012
    Assignee: Network Appliance, Inc.
    Inventors: Alexander D. Petruncola, Nareshkumar M. Patel, Grace Ho, Jeffrey S. Kimmel
  • Patent number: 7451167
    Abstract: A storage server provides a set of client devices with access to a set of mass storage devices. The storage server receives requests from the client devices, each request representing a storage operation to be performed by the storage server on the set of mass storage devices. The storage server maintains a log of write requests received from the client devices, the log including a separate log entry for each of the write requests, and a separate checksum in each of the log entries. Each checksum is for use by a checksum algorithm in determining data integrity of the corresponding log entry. The checksum algorithm is selected, from among a number of selectable a checksum algorithms, based on one or more predetermined criteria, such as a desired balance between performance and checksum strength.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: November 11, 2008
    Assignee: Network Appliance, Inc.
    Inventors: Naveen Bali, Raymond C. Chen, Kayuri Patel, Alexander D. Petruncola
  • Patent number: 5872963
    Abstract: A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: February 16, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan, Alexander D. Petruncola, David Craig