Patents by Inventor ALEXANDER DODD BRESLOW

ALEXANDER DODD BRESLOW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11138015
    Abstract: A compute unit includes single-instruction-multiple-data (SIMD) lanes that implement a pipeline. The compute unit also includes a scheduler to schedule the SIMD lanes to apply a binary associative operation to pairs of elements associated with ordered sets of elements. Subsets of the SIMD lanes concurrently apply the binary associative operation to pairs of elements at different levels of upsweep trees associated with the ordered sets of elements. Application of the binary associative operation is used to perform a reduction operation or a scan operation on the ordered sets of elements. In the case of a scan operation, the scheduler schedules the SIMD lanes to concurrently apply the binary associative operation to pairs of elements at different levels of downsweep trees associated with the ordered sets of elements subsequent to applying the binary associative operation at different levels of the upsweep trees.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Alexander Dodd Breslow
  • Patent number: 11073995
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: July 27, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander Dodd Breslow
  • Publication number: 20210072999
    Abstract: A compute unit includes single-instruction-multiple-data (SIMD) lanes that implement a pipeline. The compute unit also includes a scheduler to schedule the SIMD lanes to apply a binary associative operation to pairs of elements associated with ordered sets of elements. Subsets of the SIMD lanes concurrently apply the binary associative operation to pairs of elements at different levels of upsweep trees associated with the ordered sets of elements. Application of the binary associative operation is used to perform a reduction operation or a scan operation on the ordered sets of elements. In the case of a scan operation, the scheduler schedules the SIMD lanes to concurrently apply the binary associative operation to pairs of elements at different levels of downsweep trees associated with the ordered sets of elements subsequent to applying the binary associative operation at different levels of the upsweep trees.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventor: Alexander Dodd BRESLOW
  • Publication number: 20200241775
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventor: ALEXANDER DODD BRESLOW
  • Patent number: 10628063
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander Dodd Breslow
  • Publication number: 20200065012
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventor: ALEXANDER DODD BRESLOW