Patents by Inventor Alexander E. Mericas
Alexander E. Mericas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170168832Abstract: Methods, apparatuses, and computer program products for instruction weighting for performance profiling in a group dispatch processor are described. In a particular embodiment, a post processing profiler retrieves an execution sample including an instruction address of a youngest instruction in a dispatch group that has completed execution in a group dispatch processor and a number of instructions in the dispatch group. In the particular embodiment, the post processing profiler identifies, based on the instruction address of the youngest instruction and the number of instructions in the dispatch group, all of the instructions that are in the dispatch group at the time that the dispatch group completes execution. In the particular embodiment, the post processing profiler applies within an execution profile, the result of the execution sample, equally to all of the identified instructions that are in the dispatch group.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: ALEXANDER E. MERICAS, MARIA L. PESANTEZ, MYSORE S. SRINIVAS
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Publication number: 20170168833Abstract: Methods, apparatuses, and computer program products for instruction weighting for performance profiling in a group dispatch processor are described. In a particular embodiment, a post processing profiler retrieves an execution sample including an instruction address of a youngest instruction in a dispatch group that has completed execution in a group dispatch processor and a number of instructions in the dispatch group. In the particular embodiment, the post processing profiler identifies, based on the instruction address of the youngest instruction and the number of instructions in the dispatch group, all of the instructions that are in the dispatch group at the time that the dispatch group completes execution. In the particular embodiment, the post processing profiler applies within an execution profile, the result of the execution sample, equally to all of the identified instructions that are in the dispatch group.Type: ApplicationFiled: February 16, 2016Publication date: June 15, 2017Inventors: ALEXANDER E. MERICAS, MARIA L. PESANTEZ, MYSORE S. SRINIVAS
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Patent number: 9495170Abstract: During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.Type: GrantFiled: December 11, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat R. Indukuru, Brian R. Konigsburg, Alexander E. Mericas, Benjamin W. Stolt
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Patent number: 9405548Abstract: Methods, systems, and computer program products may provide delay-identification in data processing systems. An apparatus may include a delay-identification unit having a delay counter, a threshold register, a delay register, and a delay detector. The delay detector may be configured to start the delay counter in response to detecting that one group of instructions is delayed, and stop the delay counter in response to detecting that the one group of instructions is no longer delayed. The delay detector may additionally be configured to compare the number of cycles counted by the delay counter with a threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.Type: GrantFiled: December 7, 2011Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Venkat R Indukuru, Alexander E Mericas
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Patent number: 9229745Abstract: A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.Type: GrantFiled: September 12, 2012Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Venkat R. Indukuru, Alexander E. Mericas, Satish K. Sadasivam, Madhavi G. Valluri
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Patent number: 9229746Abstract: A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.Type: GrantFiled: December 18, 2013Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Venkat R. Indukuru, Alexander E. Mericas, Satish K. Sadasivam, Madhavi G. Valluri
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Publication number: 20140108770Abstract: A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Inventors: Venkat R. Indukuru, Alexander E. Mericas, Satish K. Sadasivam, Madhavi G. Valluri
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Publication number: 20140101416Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: VENKAT R. INDUKURU, BRIAN R. KONIGSBURG, ALEXANDER E. MERICAS, BENJAMIN W. STOLT
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Publication number: 20140075164Abstract: A method and system are disclosed for sampling instructions executing on a computer processor. A computer processor determines a number of times a specified event has occurred within a specified temporal window. The computer processor determines to mark an instruction to be executed for monitoring based on the number of times the specified event has occurred within the temporal window, and in response, the computer processor marks the instruction.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat R. Indukuru, Alexander E. Mericas
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Publication number: 20140075158Abstract: A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat R. Indukuru, Alexander E. Mericas, Satish K. Sadasivam, Madhavi G. Valluri
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Patent number: 8635436Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: GrantFiled: April 29, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Venkat R. Indukuru, Brian R. Konigsburg, Alexander E. Mericas, Benjamin W. Stolt
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Patent number: 8514999Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.Type: GrantFiled: December 6, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Giles R. Frazier, Venkat R. Indukuru, Alexander E. Mericas, John F. Spannaus
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Publication number: 20130151816Abstract: Methods, systems, and computer program products may provide delay-identification in data processing systems. An apparatus may include a delay-identification unit having a delay counter, a threshold register, a delay register, and a delay detector. The delay detector may be configured to start the delay counter in response to detecting that one group of instructions is delayed, and stop the delay counter in response to detecting that the one group of instructions is no longer delayed. The delay detector may additionally be configured to compare the number of cycles counted by the delay counter with a threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat R. Indukuru, Alexander E. Mericas
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Publication number: 20130142301Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giles R. Frazier, Venkat R. Indukuru, Alexander E. Mericas, John F. Spannaus
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Publication number: 20120278595Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: VENKAT R. INDUKURU, BRIAN R. KONIGSBURG, ALEXANDER E. MERICAS, BENJAMIN W. STOLT
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Publication number: 20110302395Abstract: A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald P. Hall, Venkat R. Indukuru, Alexander E. Mericas, Balaram Sinharoy, Zhong L. Wang
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Patent number: 7992051Abstract: An apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.Type: GrantFiled: September 9, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Ra'ed M. Al-Omari, Alexander E. Mericas, William J. Starke
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Patent number: 7844860Abstract: An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.Type: GrantFiled: August 29, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Ra'ed M. Al-Omari, Alexander E. Mericas, William J. Starke
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Publication number: 20090276190Abstract: A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Bell, JR., Thomas W. Chen, Venkat R. Indukuru, Alexander E. Mericas, Pattabi M. Seshadri, Madhavi G. Valluri
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Publication number: 20090106539Abstract: In a data processing system having a set of components for performing a set of operations, in which one or more of the set of operations has processing dependencies with respect to other of the set of operations, a method for using an additive stall counter to analyze a completion delay is disclosed. The method includes initiating execution of a group of instructions and a performance monitor unit resetting a value stored within the additive stall counter. The method further includes the performance monitor unit incrementing the value within the additive stall counter until all instructions within the group of instructions complete. In response to all instructions within the group of instructions completing a cause of the completion delay is determined.Type: ApplicationFiled: July 5, 2007Publication date: April 23, 2009Inventor: ALEXANDER E. MERICAS