Abstract: Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be determined, for example, from the availability of the data without a bus transaction. The capability of accelerating data in this fashion requires only a few simple changes in processor state transitions, required to permit entry of the data completion wait state prior to the response wait state. Processors may forward accelerated data to execution units with the expectation that a null snoop response will be received during the coherency response window. If a non-null snoop response is received, an error condition is asserted. Data acceleration of the type described allows critical data to get back to the processor without waiting for the coherency response window.

Abstract: A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed.

Abstract: A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache.

Abstract: Data loaded from system memory to a cache within a multiprocessor system is set to the exclusive coherency state if no other cache or processor has a copy of that data. Subsequent accesses to the data by another processor or cache which are snooped by the data owner result in an exclusive intervention by the data owner. The data owner sources the data to and shares the data with the requesting device on a read and transfers exclusive ownership of the data to the requesting device on a read with intent to modify. Unmodified intervention with cache-to-cache transfers over possibly much slower accesses to memory is thus supported by the multiprocessor system without requiring additional tag or status bits in the cache directories, saving a significant area.

Abstract: Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.

Abstract: Described is an apparatus for eliminating early retrying of PAAM address conflicts on a system bus with multiple processors connected by a non-master processor, by comparing addresses of the current master processor to the next transaction to be issued by the non-master processor. If the addresses are the same and a PAAM window is detected, the non-master processor will switch the next transaction type to be issued, to a null type transaction. Even though the addresses match, the PAAM window is ignored for a null type transaction. The null transaction type insertion by the non-master processor reduces the latency of a PAAM self retried operation and avoids a possible livelock condition by breaking the processors out of the livelock. This allows the processors to stop retrying and leave the bus. The processors are able to immediately arbitrate instead of delaying past the astat window and increasing bus latency.