Patents by Inventor Alexander Fuad Ashkar
Alexander Fuad Ashkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087078Abstract: Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.Type: ApplicationFiled: June 19, 2023Publication date: March 14, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Vishrut Vaibhav, Manu Rastogi, Harry J. Wise
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Patent number: 11900123Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.Type: GrantFiled: December 13, 2019Date of Patent: February 13, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Manu Rastogi, Harry J. Wise
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Patent number: 11900499Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.Type: GrantFiled: September 22, 2020Date of Patent: February 13, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh Rajendra Acharya, Ruijin Wu, Alexander Fuad Ashkar, Harry J. Wise
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Patent number: 11809558Abstract: A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.Type: GrantFiled: September 25, 2020Date of Patent: November 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Wise, Alexander Fuad Ashkar, Manu Rastogi
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Patent number: 11782838Abstract: Techniques for prefetching are provided. The techniques include receiving a first prefetch command; in response to determining that a history buffer indicates that first information associated with the first prefetch command has not already been prefetched, prefetching the first information into a memory; receiving a second prefetch command; and in response to determining that the history buffer indicates that second information associated with the second prefetch command has already been prefetched, avoiding prefetching the second information into the memory.Type: GrantFiled: March 31, 2021Date of Patent: October 10, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Alexander Fuad Ashkar
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Publication number: 20230206379Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Mangesh P. Nijasure, Rakan Z. Khraisha, Manu Rastogi
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Patent number: 11579876Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.Type: GrantFiled: August 31, 2020Date of Patent: February 14, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Anirudh R. Acharya, Alexander Fuad Ashkar, Ashkan Hosseinzadeh Namin
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Patent number: 11537319Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.Type: GrantFiled: December 11, 2019Date of Patent: December 27, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Fuad Ashkar, James R. Klobcar, Harry J. Wise
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Patent number: 11386518Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.Type: GrantFiled: September 24, 2019Date of Patent: July 12, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Michael Mantor, Alexander Fuad Ashkar, Randy Ramsey, Mangesh P. Nijasure, Brian Emberling
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Publication number: 20220100856Abstract: A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Harry J. WISE, Alexander FUAD ASHKAR, Manu RASTOGI
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Publication number: 20220091847Abstract: In response to executing a specified command packet, a processing unit prefetches commands stored at an indirect buffer a command queue for execution, prior to executing a command that initiates execution of the commands stored at the indirect buffer. By prefetching the data prior to executing the indirect buffer execution command, the processing unit reduces delays in processing the commands stored at the indirect buffer.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Alexander Fuad ASHKAR, Harry J. WISE, Rex Eldon MCCRARY, Hans FERNLUND
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Publication number: 20220050781Abstract: Techniques for prefetching are provided. The techniques include receiving a first prefetch command; in response to determining that a history buffer indicates that first information associated with the first prefetch command has not already been prefetched, prefetching the first information into a memory; receiving a second prefetch command; and in response to determining that the history buffer indicates that second information associated with the second prefetch command has already been prefetched, avoiding prefetching the second information into the memory.Type: ApplicationFiled: March 31, 2021Publication date: February 17, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Alexander Fuad Ashkar
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Publication number: 20220043653Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.Type: ApplicationFiled: August 31, 2020Publication date: February 10, 2022Inventors: Anirudh R. ACHARYA, Alexander Fuad ASHKAR, Ashkan HOSSEINZADEH NAMIN
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Patent number: 11243799Abstract: An apparatus includes a plurality of virtual machines, a hypervisor coupled to the plurality of virtual machines, and a graphical processing unit (GPU) coupled to the hypervisor. The plurality of virtual machines are allocated a plurality of time slices. The hypervisor initiates a world switch to a first virtual machine of the plurality of virtual machines. The GPU makes a determination as to whether to adjust the time slice associated with the first virtual machine based on an assessment of time slice adjustment parameters related to an execution time of at least one of the plurality of virtual machines.Type: GrantFiled: August 30, 2019Date of Patent: February 8, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Hans Fernlund
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Patent number: 11169811Abstract: A method of context bouncing includes receiving, at a command processor of a graphics processing unit (GPU), a conditional execute packet providing a hash identifier corresponding to an encapsulated state. The encapsulated state includes one or more context state packets following the conditional execute packet. A command packet following the encapsulated state is executed based at least in part on determining whether the hash identifier of the encapsulated state matches one of a plurality of hash identifiers of active context states currently stored at the GPU.Type: GrantFiled: May 30, 2019Date of Patent: November 9, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Rex Eldon McCrary, Yi Luo, Harry J. Wise, Alexander Fuad Ashkar, Michael Mantor
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Patent number: 11144329Abstract: A processing unit employs microcode wherein the jump table associated with the microcode is embedded in the microcode itself. When the microcode is compiled based on a set of programmer instructions, the compiler prepares the jump table for the microcode and stores the jump table in the same file or other storage unit as the microcode. When the processing unit is initialized to execute a program, such as an operating system, the processing unit retrieves the microcode corresponding to the program from memory, stores the microcode in a cache or other memory module for execution, and automatically loads the embedded jump table from the microcode to a specified set of jump table registers, thereby preparing the processing unit to process received packets.Type: GrantFiled: May 31, 2019Date of Patent: October 12, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Fuad Ashkar, Rakan Khraisha, Rex Eldon McCrary, Harry J. Wise
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Publication number: 20210304349Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.Type: ApplicationFiled: September 22, 2020Publication date: September 30, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Anirudh Rajendra Acharya, Ruijin Wu, Alexander Fuad Ashkar, Harry J. Wise
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Publication number: 20210181973Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.Type: ApplicationFiled: December 11, 2019Publication date: June 17, 2021Inventors: Alexander Fuad ASHKAR, James R. KLOBCAR, Harry J. WISE
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Publication number: 20210182072Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Alexander Fuad ASHKAR, Manu RASTOGI, Harry J. WISE
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Publication number: 20210090205Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: Michael MANTOR, Alexander Fuad ASHKAR, Randy RAMSEY, Mangesh P. NIJASURE, Brian EMBERLING