Patents by Inventor Alexander Garner

Alexander Garner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9178100
    Abstract: A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 3, 2015
    Assignees: STMicroelectronics (Research & Development) Limited, The University Court of the University of Edinburgh
    Inventors: Eric Alexander Garner Webster, Robert Kerr Henderson
  • Publication number: 20140191115
    Abstract: A deep SPAD structure uses the substrate as the anode terminal of its multiplication p-n junction. A bias voltage for the SPAD (in excess of the SPAD's breakdown voltage) is coupled to the SPAD's cathode terminal. The bias voltage is generated by a charge pump circuit which is also integrated on the substrate. The charge pump circuit is configured to isolate the bias voltage on the cathode terminal. A triple well CMOS process is used to isolate the transistors of the charge pump circuit from the substrate.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 10, 2014
    Applicants: THE UNIVERSITY COURT OF THE UNIERSITY OF EDINBURGH, STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Eric Alexander Garner Webster, Robert K. Henderson
  • Publication number: 20130193546
    Abstract: A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.
    Type: Application
    Filed: September 8, 2011
    Publication date: August 1, 2013
    Applicant: The University Court of the University of Edinburg
    Inventors: Eric Alexander Garner Webster, Robert Kerr Henderson
  • Patent number: D689375
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: September 10, 2013
    Inventor: Alexander Garner
  • Patent number: D690161
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 24, 2013
    Inventor: Alexander Garner