Patents by Inventor Alexander Gendler

Alexander Gendler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200333867
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 22, 2020
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Patent number: 10809790
    Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Yiftach Gilad, Ariel Szapiro, Elkana Korem, Alexander Gendler
  • Publication number: 20200310509
    Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Gendler, Elkana Korem, Hanan Shomroni, Nadav Shulman
  • Publication number: 20200310511
    Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
  • Publication number: 20200310872
    Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
  • Publication number: 20200310527
    Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.
    Type: Application
    Filed: March 30, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Gendler, Yoni Aizik, Chen Ranel, Ido Melamed, Edward Vaiberman
  • Patent number: 10775434
    Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Larisa Novakovsky, Edward Brazil, Alexander Gendler
  • Publication number: 20200272220
    Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Inventors: Praveen MOSALIKANTI, Nasser KURD, Alexander GENDLER
  • Patent number: 10719326
    Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
  • Patent number: 10705559
    Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Alexander Gendler, Kosta Luria, Arye Albahari, Ohad Nachshon
  • Patent number: 10663998
    Abstract: Various embodiments provide a voltage regulator circuit with automatic phase shedding. A control circuit may control first transitions of a power state of the voltage regulator based on an average current draw of the voltage regulator. The control circuit may further control second transitions of the power state of the voltage regulator based on a voltage droop of the output voltage and/or a peak current draw of the voltage regulator. The first transitions may be performed synchronously, and the second transitions may be performed asynchronously. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Tamir Salus, Alexander Lyakhov, Alexander Gendler, Krishnakanth Sistla, Ankush Varma, Rachid Rayess, Nimrod Angel
  • Publication number: 20200125365
    Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Alexander Gendler, Eliezer Weissmann, Michael Mishaeli
  • Patent number: 10628542
    Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
  • Publication number: 20200110460
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: July 16, 2019
    Publication date: April 9, 2020
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Patent number: 10613611
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Publication number: 20200096569
    Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Michael Mishaeli, Larisa Novakovsky, Edward Brazil, Alexander Gendler
  • Publication number: 20200012333
    Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Inventors: Alexander Gendler, Arkady Bramnik, Lev Makovsky
  • Patent number: 10503509
    Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Eliezer Weissmann, Michael Mishaeli
  • Publication number: 20190370209
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Publication number: 20190346878
    Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
    Type: Application
    Filed: November 13, 2018
    Publication date: November 14, 2019
    Inventors: Alexander Gendler, Kosta Luria, Arye Albahari, Ohad Nachshon