Abstract: The present invention provides a system and method of optical communications that utilize coherent detection technique and optical orthogonal frequency division multiplexing for phase encoded data transmission. In particular the invention addresses a device and method for digital polarization compensation of optical signals with up to 100 Gb/s transmission rate received via an optical link. The polarization compensation operates in two modes: acquisition mode and tracking mode. The polarization recovery is performed at the receiver side using the received digital signal conversion into frequency domain and separate reconstruction of the polarization state in each spectral component.

Abstract: The present invention provides a system and method of optical communications that utilize coherent detection technique and optical orthogonal frequency division multiplexing for phase encoded data transmission. In particular the invention addresses a device and method for digital polarization compensation of optical signals with up to 100 Gb/s transmission rate received via an optical link. The polarization compensation operates in two modes: acquisition mode and tracking mode. The polarization recovery is performed at the receiver side using the received digital signal conversion into frequency domain and separate reconstruction of the polarization state in each spectral component.

Abstract: A concurrent vector signal processor includes a resource manager for utilization of captive signal processing resources. The first instructions in a temporary instruction queue are predecoded and the signal processing resources are selected to execute those first instructions.Arbitration system is provided for external buses connected to a concurrent vector signal processor. A processor arbiter supervises on a priority basis both captive processor resources and independent processor resources. A bus arbiter supervises on a priority basis external and internal buses.

Abstract: Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.

Abstract: An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands.