Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

Abstract: A math device has a multiplier and an overflow detector. The multiplier multiplies an n-bit input with an m-bit input and produces a reduced width output without producing an intervening data file having a width greater than or equal to n+m. The overflow detector determines if the reduced width output eliminates non-redundant bits. According to a second aspect, the overflow detector determines when the product of the m-bit input and the n-bit input would exceed o-bits, where o<(m+n), the overflow detector having a first overflow unit provided in parallel to the multiplier, and a second overflow unit provided in series with the multiplier. According to a third aspect, the overflow detector has a comparator provided on a critical timing path, and the comparator requires only a review of 4 bits.