Patents by Inventor Alexander Heilmaier

Alexander Heilmaier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220080549
    Abstract: Semiconductor wafers are polished simultaneously on both the front and the rear sides between an upper polishing plate and a lower polishing plate, each covered with a polishing pad, wherein a polishing gap (x1+x2) corresponding to a difference in the respective distances between facing surfaces of upper polishing pad and lower polishing pad which come into contact with the semiconductor wafer at the inner edge and at the outer edge of the polishing pads is changed incrementally or continuously during the polishing process.
    Type: Application
    Filed: February 5, 2019
    Publication date: March 17, 2022
    Applicant: SILTRONIC AG
    Inventors: Alexander HEILMAIER, Vladimir DUTSCHKE, Leszek MISTUR, Torsten OLBRICH, Dirk MEYER, Vincent NG
  • Patent number: 10189142
    Abstract: A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: January 29, 2019
    Assignee: SILTRONIC AG
    Inventors: Klaus Roettger, Alexander Heilmaier, Leszek Mistur, Makoto Tabata, Vladimir Dutschke, Torsten Olbrich
  • Patent number: 9221149
    Abstract: A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: December 29, 2015
    Assignee: SILTRONIC AG
    Inventors: Rainer Baumann, Johannes Staudhammer, Alexander Heilmaier, Leszek Mistur, Klaus Roettger
  • Publication number: 20140308878
    Abstract: A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 16, 2014
    Applicant: Siltronic AG
    Inventors: Rainer Baumann, Johannes Staudhammer, Alexander Heilmaier, Leszek Mistur, Klaus Roettger
  • Publication number: 20140206261
    Abstract: A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.
    Type: Application
    Filed: November 29, 2013
    Publication date: July 24, 2014
    Applicant: Siltronic AG
    Inventors: Klaus Roettger, Alexander Heilmaier, Leszek Mistur, Makoto Tabata, Vladimir Dutschke, Torsten Olbrich
  • Publication number: 20140141613
    Abstract: A process for polishing a semiconductor wafer includes simultaneous polishing of a front side and of a reverse side of a substrate wafer in the presence of polishing medium so as to achieve material removal from the front side and the reverse side of the substrate wafer. The simultaneous polishing includes a first step and a second step. A speed of material removal in the first step is higher than in the second step. The first step includes the use of a first polishing slurry as a polishing medium and the second step includes a second polishing slurry as the polishing medium. The second polishing slurry differs from the first polishing slurry at least in that the second polishing slurry comprises a polymeric additive.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: Siltronic AG
    Inventors: Alexander Heilmaier, Leszek Mistur, Klaus Roettger, Makoto Tabata
  • Patent number: 8242020
    Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 14, 2012
    Assignee: Siltronic AG
    Inventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
  • Patent number: 7766724
    Abstract: Slicing multiple cylindrical workpieces into wafers by a multi wire saw with a gang length LG, is performed by: a) selecting a number n?2 of workpieces from a stock of workpieces with different lengths, satisfying the inequality L G ? ( n - 1 ) · A min + ? i = 1 n ? ? L 1 ( 1 ) and making right-hand side of the inequality as large as possible, where Li with i=1 . . . n are for the lengths of the workpieces and Amin is a predefined minimum spacing, b) fixing the n workpieces successively in the longitudinal direction on a mounting plate while maintaining a spacing A?Amin therebetween such that the relationship L G ? ( n - 1 ) · A + ? i = 1 n ? ? L i ( 2 ) is satisfied, c) clamping mounting plates workpieces in a multi wire saw, and d) slicing the n workpieces perpendicularly to their longitudinal axis by means of the multi wire saw.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: August 3, 2010
    Assignee: Siltronic AG
    Inventors: Anton Huber, Alexander Heilmaier, Clemens Radspieler, Helmut Seehofer
  • Publication number: 20100055908
    Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 4, 2010
    Applicant: Siltronic AG
    Inventors: Klaus Roettger, Gerhard Heier, Alexander Heilmaier
  • Publication number: 20080099006
    Abstract: Slicing multiple cylindrical workpieces into wafers by a multi wire saw with a gang length LG, is performed by: a) selecting a number n?2 of workpieces from a stock of workpieces with different lengths, satisfying the inequality L G ? ( n - 1 ) · A min + ? i = 1 n ? ? L 1 ( 1 ) and making right-hand side of the inequality as large as possible, where Li with i=1 . . . n are for the lengths of the workpieces and Amin is a predefined minimum spacing, b) fixing the n workpieces successively in the longitudinal direction on a mounting plate while maintaining a spacing A?Amin therebetween such that the relationship L G ? ( n - 1 ) · A + ? i = 1 n ? ? L i ( 2 ) is satisfied, c) clamping mounting plates workpieces in a multi wire saw, and d) slicing the n workpieces perpendicularly to their longitudinal axis by means of the multi wire saw.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 1, 2008
    Applicant: SILTRONIC AG
    Inventors: Anton Huber, Alexander Heilmaier, Clemens Radspieler, Helmut Seehofer
  • Publication number: 20060211338
    Abstract: The invention relates to a method for removing material from a semiconductor wafer by machining, in which a semiconductor wafer held on a wafer holder and a grinding wheel lying opposite it are rotated independently of one another, the grinding wheel being arranged laterally offset with respect to the semiconductor wafer and being positioned in such a way that an axial center of the semiconductor wafer passes into a working range of the grinding wheel, the grinding wheel being moved in the direction of the semiconductor wafer at an infeed rate, with the result that grinding wheel and semiconductor wafer are advanced toward one another while the semiconductor wafer and grinding wheel are rotating about parallel axes, so that a surface of the semiconductor wafer is ground, with the grinding wheel being moved back at a return rate after a defined amount of material has been removed, wherein the grinding wheel and semiconductor wafer are advanced toward one another by a distance of 0.03-0.
    Type: Application
    Filed: March 16, 2006
    Publication date: September 21, 2006
    Inventors: Alexander Heilmaier, Robert Drexler, Anton Huber, Robert Weiss
  • Patent number: 7108583
    Abstract: The invention relates to a method for removing material from a semiconductor wafer by machining, in which a semiconductor wafer held on a wafer holder and a grinding wheel lying opposite it are rotated independently of one another, the grinding wheel being arranged laterally offset with respect to the semiconductor wafer and being positioned in such a way that an axial center of the semiconductor wafer passes into a working range of the grinding wheel, the grinding wheel being moved in the direction of the semiconductor wafer at an infeed rate, with the result that grinding wheel and semiconductor wafer are advanced toward one another while the semiconductor wafer and grinding wheel are rotating about parallel axes, so that a surface of the semiconductor wafer is ground, with the grinding wheel being moved back at a return rate after a defined amount of material has been removed, wherein the grinding wheel and semiconductor wafer are advanced toward one another by a distance of 0.03–0.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: September 19, 2006
    Assignee: Siltronic AG
    Inventors: Alexander Heilmaier, Robert Drexler, Anton Huber, Robert Weiss
  • Patent number: 6861360
    Abstract: A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQRmax of less than or equal to 0.13 ?m, based on a surface grid of segments with a size of 26 mm×8 mm on the front surface, wherein the maximum local height deviation P/V(10×10)max of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×10 mm.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: March 1, 2005
    Assignee: Siltronic AG
    Inventors: Guido Wenski, Thomas Altmann, Anton Huber, Alexander Heilmaier
  • Publication number: 20030109139
    Abstract: A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQRm-1 of less than or equal to 0.13 &mgr;m, based on a surface grid of segments with a size of 26 mm×8 mm on the front surface, wherein the maximum local height deviation P/V(10×10)m-1 of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×10 mm.
    Type: Application
    Filed: November 14, 2002
    Publication date: June 12, 2003
    Inventors: Guido Wenski, Thomas Altmann, Anton Huber, Alexander Heilmaier