Abstract: An apparatus and method for performing multiply-accumulate operations.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein that mitigate hard-braking events. An example apparatus includes a world generator to generate a deep learning model to identify and categorize an object in a proximity of a vehicle, a data analyzer to determine a danger level associated with the object, the danger level indicative of a likelihood of a collision between the vehicle and the object, a vehicle response determiner to determine, based on the danger level, a response of the vehicle to avoid a collision with the object, and an instruction generator to transmit instructions to a steering system or a braking system of the vehicle based on the determined vehicle response.

Abstract: An apparatus and method down-converting and interleaving data elements.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus to analyze vehicle perspectives, the apparatus comprising a profile generator to generate a first profile of an environment based on a profile template and first data generated by a first vehicle; a data analyzer to: determine a difference between the first profile and a second profile obtained from a first one of one or more nodes in the environment; and in response to a trigger event, update the first profile based on the difference; and a vehicle control system to: in response to the trigger event, update a first perspective of the environment based on one or more of second data from the first one of the one or more nodes or the updated first profile; update a path plan for the first vehicle based on the updated first perspective; and execute the updated path plan.

Abstract: Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.

Abstract: An apparatus includes a data interface to obtain first sensor data from a first sensor and second sensor data from a second sensor of a monitored system; a data analyzer to extract a feature based on analyzing the first and second sensor data using a model, the model trained based on historical sensor data, the model to determine the feature as a deviation between the first and second sensor data to predict a future malfunction of the monitored system; an anomaly detector to detect an anomaly in at least one of the first sensor data or the second sensor data based on the feature, the anomaly corresponding to the future malfunction of the monitored system; and a system applicator to modify operation of the monitored system based on the anomaly.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example system includes a memory accessed by a program of interest, a performance monitoring unit to collect first memory access information and second memory access information about an object accessed in the memory by the program of interest; and a leak detector to: determine a non-access period based on the first memory access information and an unsupervised machine learning model trained based on the program of interest; and detect a potential memory leak of the program of interest based on the second memory access information and the non-access period.

Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.

Abstract: An apparatus and method for efficient matrix alignment in a systolic array.

Abstract: Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

Abstract: An apparatus and method for performing multiply-accumulate operations.

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.

Abstract: Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a quadword data elements of a matrix pair. Additionally, in some instances, non-accumulating quadword data elements of the matrix pair are set to zero.

Abstract: Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.

Abstract: Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.