Patents by Inventor Alexander Heubi
Alexander Heubi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881817Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.Type: GrantFiled: June 10, 2022Date of Patent: January 23, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sinisa Milicevic, Alexander Heubi, Noureddine Senouci
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Publication number: 20230284926Abstract: A sensor circuit includes a transimpedance amplifier, a feedback network, and a readout circuit. The transimpedance amplifier has a first input for receiving a measured signal, a second input for receiving a reference signal, and an output. The feedback network includes a capacitor and a variable resistor each coupled between the output and the first input of the transimpedance amplifier. The readout circuit is coupled to the feedback network and has an output for providing a readout signal. In a conversion mode, the readout circuit provides the readout signal based on one sample of the output of the transimpedance amplifier. In an integration mode, the readout circuit provides the readout signal based on a plurality of samples of the output of the transimpedance amplifier.Type: ApplicationFiled: August 19, 2022Publication date: September 14, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moez KANOUN, Abdullah AHMED, Jonas WEILAND, Alexander HEUBI
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Patent number: 11742857Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.Type: GrantFiled: July 5, 2022Date of Patent: August 29, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander Heubi
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Patent number: 11705901Abstract: A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.Type: GrantFiled: June 8, 2022Date of Patent: July 18, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander Heubi
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Publication number: 20230053626Abstract: A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.Type: ApplicationFiled: March 31, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Onur KAZANC, Alexander HEUBI, Noureddine SENOUCI
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Publication number: 20230060017Abstract: A near-field transmitter includes a power amplifier, a resonant network, an envelope detector, and an antenna tuning circuit. The power amplifier has an input for receiving a communication signal, and an output for providing a differential output signal. The resonant network is coupled to the output of the power amplifier and has a tunable reactive element tuned by a tuning signal. The envelope detector is coupled to the output of the power amplifier for providing an envelope signal in response to the differential output signal. The antenna tuning circuit is for adjusting the tuning signal in response to the envelope signal.Type: ApplicationFiled: August 3, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Noureddine SENOUCI, Alexander HEUBI
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Publication number: 20230057051Abstract: A high voltage is generated from a low supply voltage by a charge pump driven with a pulse generator. A comparator compares the low supply voltage to a predetermined proportion of the high voltage. A low power voltage divider creates the predetermined portion of the high voltage. The comparator output drives the pulse generator, and the pulse generator output resets the comparator. A high voltage to low voltage mode may also be employed using the same arrangement.Type: ApplicationFiled: August 3, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander HEUBI
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Publication number: 20230056841Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.Type: ApplicationFiled: June 10, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sinisa MILICEVIC, Alexander HEUBI, Noureddine SENOUCI
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Publication number: 20230054955Abstract: A low-dropout linear regulator regulates a supply voltage and includes a voltage-to-frequency circuit producing a pulse chain with a frequency based on an error voltage. A charge pump circuit receives the pulse chain and switching one or more charge pumps based on the pulse chain. A current mirror circuit is connected to the charge pump circuit and includes a first diode-connected metal-oxide semiconductor (MOS) transistor, and a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output, and a gate connected to the gate of the first MOS transistor. The output is fed back to the voltage-to-frequency circuit.Type: ApplicationFiled: June 16, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander HEUBI
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Publication number: 20230058757Abstract: A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.Type: ApplicationFiled: June 8, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander HEUBI
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Publication number: 20230060082Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.Type: ApplicationFiled: July 5, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander HEUBI
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Publication number: 20230055295Abstract: A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.Type: ApplicationFiled: May 16, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Alexander HEUBI, Onur KAZANC
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Publication number: 20230060050Abstract: A low noise amplifier includes a plurality of serially-coupled amplifier stages. Each serially-coupled amplifier stage provides a respective amplified signal, wherein a first amplifier stage receives an input signal, and a last amplifier stage provides an amplified output signal. Each serially-coupled amplifier stage includes a single-ended amplifier having an input, and an output providing the respective amplified signal, a first passive network, and a second passive network. The first passive network has a first terminal forming an input of a respective one of said plurality of serially-coupled amplifier stages, and a second terminal coupled to said input of said single-ended amplifier, the first passive network including a first capacitor coupled in series between the first and said second terminals of the first passive network. The second passive network is coupled in parallel to the single-ended amplifier and between the input and the output of the single-ended amplifier.Type: ApplicationFiled: March 31, 2022Publication date: February 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Noureddine SENOUCI, Onur KAZANC, Alexander HEUBI
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Patent number: 10305319Abstract: According to an aspect, an electronic device includes a switching converter configured to generate an output voltage with a first voltage level from a battery voltage in a run mode of the electronic device. The switching converter is configured to generate the output voltage with a second voltage level from the battery voltage in a sleep mode of the electronic device. The second voltage level is less than the first voltage level. The switching converter includes a clocked comparator, and a voltage comparator. The switching converter is configured to generate the output voltage with the first voltage level in the run mode using the clocked comparator. The switching converter is configured to generate the output voltage with the second voltage level in the sleep mode using the voltage comparator.Type: GrantFiled: May 8, 2018Date of Patent: May 28, 2019Assignee: Semiconductor Components Industries, LLCInventor: Alexander Heubi
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Publication number: 20190067984Abstract: According to an aspect, an electronic device includes a switching converter configured to generate an output voltage with a first voltage level from a battery voltage in a run mode of the electronic device. The switching converter is configured to generate the output voltage with a second voltage level from the battery voltage in a sleep mode of the electronic device. The second voltage level is less than the first voltage level. The switching converter includes a clocked comparator, and a voltage comparator. The switching converter is configured to generate the output voltage with the first voltage level in the run mode using the clocked comparator. The switching converter is configured to generate the output voltage with the second voltage level in the sleep mode using the voltage comparator.Type: ApplicationFiled: May 8, 2018Publication date: February 28, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander HEUBI
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Patent number: 10117035Abstract: An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.Type: GrantFiled: January 11, 2018Date of Patent: October 30, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ivo Leonardus Coenen, Alexander Heubi
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Patent number: 10050637Abstract: A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input signal and a feedback signal; an integrator, coupled to the differentiator, to integrate the differentiated signal; a quantizer, coupled to the integrator, to quantize the integrated signal; and a low-pass feedback filter, coupled between an output of the quantizer and an input of the differentiator, to generate said feedback signal using the quantized signal, wherein the low-pass feedback filter pushes at least some noise of the quantized signal downward in the frequency spectrum.Type: GrantFiled: August 25, 2017Date of Patent: August 14, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander Heubi
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Publication number: 20180139550Abstract: An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ivo Leonardus COENEN, Alexander HEUBI
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Patent number: 9918172Abstract: An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.Type: GrantFiled: August 19, 2016Date of Patent: March 13, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ivo Leonardus Coenen, Alexander Heubi
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Publication number: 20180054684Abstract: An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.Type: ApplicationFiled: August 19, 2016Publication date: February 22, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ivo Leonardus COENEN, Alexander HEUBI