Abstract: Audio communication methods, devices, and systems are provided with an ultra-low latency communications protocol. One illustrative communication method suitable for a primary hearing instrument includes: transmitting a preamble packet to initiate a wireless connection; after receiving a preamble response packet, wirelessly sending a downlink stream of audio data frames; and wirelessly receiving an uplink stream of audio data frames. The audio data frames of the downlink stream and the uplink stream each consist of a message packet, a check packet, and multiple single-sample audio data packets, and these packets exclude any preambles or sync words. The audio data frame packets of the downlink stream and the uplink stream are interleaved with each other.

Abstract: A near-field transmitter includes a power amplifier, a resonant network, an envelope detector, and an antenna tuning circuit. The power amplifier has an input for receiving a communication signal, and an output for providing a differential output signal. The resonant network is coupled to the output of the power amplifier and has a tunable reactive element tuned by a tuning signal. The envelope detector is coupled to the output of the power amplifier for providing an envelope signal in response to the differential output signal. The antenna tuning circuit is for adjusting the tuning signal in response to the envelope signal.

Abstract: A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.

Abstract: A low noise amplifier includes a plurality of serially-coupled amplifier stages. Each serially-coupled amplifier stage provides a respective amplified signal, wherein a first amplifier stage receives an input signal, and a last amplifier stage provides an amplified output signal. Each serially-coupled amplifier stage includes a single-ended amplifier having an input, and an output providing the respective amplified signal, a first passive network, and a second passive network. The first passive network has a first terminal forming an input of a respective one of said plurality of serially-coupled amplifier stages, and a second terminal coupled to said input of said single-ended amplifier, the first passive network including a first capacitor coupled in series between the first and said second terminals of the first passive network. The second passive network is coupled in parallel to the single-ended amplifier and between the input and the output of the single-ended amplifier.

Abstract: A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.

Abstract: Audio communication methods, devices, and systems are provided with an ultra-low latency communications protocol. One illustrative communication method suitable for a primary hearing instrument includes: transmitting a preamble packet to initiate a wireless connection; after receiving a preamble response packet, wirelessly sending a downlink stream of audio data frames; and wirelessly receiving an uplink stream of audio data frames. The audio data frames of the downlink stream and the uplink stream each consist of a message packet, a check packet, and multiple single-sample audio data packets, and these packets exclude any preambles or sync words. The audio data frame packets of the downlink stream and the uplink stream are interleaved with each other.

Abstract: A low-dropout linear regulator regulates a supply voltage and includes a voltage-to-frequency circuit producing a pulse chain with a frequency based on an error voltage. A charge pump circuit receives the pulse chain and switching one or more charge pumps based on the pulse chain. A current mirror circuit is connected to the charge pump circuit and includes a first diode-connected metal-oxide semiconductor (MOS) transistor, and a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output, and a gate connected to the gate of the first MOS transistor. The output is fed back to the voltage-to-frequency circuit.

Abstract: A high voltage is generated from a low supply voltage by a charge pump driven with a pulse generator. A comparator compares the low supply voltage to a predetermined proportion of the high voltage. A low power voltage divider creates the predetermined portion of the high voltage. The comparator output drives the pulse generator, and the pulse generator output resets the comparator. A high voltage to low voltage mode may also be employed using the same arrangement.

Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: A sensor circuit includes a transimpedance amplifier, a feedback network, and a readout circuit. The transimpedance amplifier has a first input for receiving a measured signal, a second input for receiving a reference signal, and an output. The feedback network includes a capacitor and a variable resistor each coupled between the output and the first input of the transimpedance amplifier. The readout circuit is coupled to the feedback network and has an output for providing a readout signal. In a conversion mode, the readout circuit provides the readout signal based on one sample of the output of the transimpedance amplifier. In an integration mode, the readout circuit provides the readout signal based on a plurality of samples of the output of the transimpedance amplifier.

Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

Abstract: A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.

Abstract: A low noise amplifier includes a plurality of serially-coupled amplifier stages. Each serially-coupled amplifier stage provides a respective amplified signal, wherein a first amplifier stage receives an input signal, and a last amplifier stage provides an amplified output signal. Each serially-coupled amplifier stage includes a single-ended amplifier having an input, and an output providing the respective amplified signal, a first passive network, and a second passive network. The first passive network has a first terminal forming an input of a respective one of said plurality of serially-coupled amplifier stages, and a second terminal coupled to said input of said single-ended amplifier, the first passive network including a first capacitor coupled in series between the first and said second terminals of the first passive network. The second passive network is coupled in parallel to the single-ended amplifier and between the input and the output of the single-ended amplifier.

Abstract: A low-dropout linear regulator regulates a supply voltage and includes a voltage-to-frequency circuit producing a pulse chain with a frequency based on an error voltage. A charge pump circuit receives the pulse chain and switching one or more charge pumps based on the pulse chain. A current mirror circuit is connected to the charge pump circuit and includes a first diode-connected metal-oxide semiconductor (MOS) transistor, and a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output, and a gate connected to the gate of the first MOS transistor. The output is fed back to the voltage-to-frequency circuit.

Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

Abstract: A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.

Abstract: A high voltage is generated from a low supply voltage by a charge pump driven with a pulse generator. A comparator compares the low supply voltage to a predetermined proportion of the high voltage. A low power voltage divider creates the predetermined portion of the high voltage. The comparator output drives the pulse generator, and the pulse generator output resets the comparator. A high voltage to low voltage mode may also be employed using the same arrangement.

Abstract: A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.

Abstract: A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.