Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link. In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.

Abstract: An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable media are also disclosed.

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Abstract: The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.