Patents by Inventor Alexander J. Branover

Alexander J. Branover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220147455
    Abstract: A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Kevin M. Lepak, William A. Moyes
  • Publication number: 20220100504
    Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Benjamin TSIEN, Alexander J. BRANOVER, John PETRY, Chen-Ping YANG, Rostyslav KYRYCHYNSKYI, Vydhyanathan KALYANASUNDHARAM
  • Patent number: 11289131
    Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
  • Publication number: 20210200298
    Abstract: Methods, devices and systems for power management in a computer processing device are disclosed. The methods may include selecting, by a data fabric, D23 as target state, selecting D3 state by a memory controller, blocking memory access, reducing data fabric and memory controller clocks, reduce SoC voltage, and turning PHY voltage off. The methods may include signaling to wake up the SoC, starting exit flow by ramping up SoC voltage and ramping data fabric and memory controller clocks, unblocking memory access, propagating activity associated with the wake up event to memory, exiting D3 by PHY, and exiting self-refresh by a memory.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Benjamin Tsien
  • Publication number: 20210191879
    Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Sonu ARORA, Benjamin TSIEN, Alexander J. BRANOVER
  • Publication number: 20210191493
    Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Jyoti Raheja, Alexander J. Branover
  • Patent number: 11036658
    Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 15, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Vydhyanathan Kalyanasundharam, Philip Ng, Alexander J Branover, Kevin M. Lepak
  • Publication number: 20210173715
    Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
  • Publication number: 20210090613
    Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
  • Patent number: 10955892
    Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jyoti Raheja, Alexander J. Branover
  • Patent number: 10949127
    Abstract: Systems, apparatuses, and methods for dynamically optimizing memory traffic in multi-client systems are disclosed. A system includes a plurality of client devices, a memory subsystem, and a communication fabric coupled to the client devices and the memory subsystem. The system includes a first client which generates memory access requests targeting the memory subsystem. Prior to sending a given memory access request to the fabric, the first client analyzes metadata associated with data targeted by the given memory access request. If the metadata indicates the targeted data is the same as or is able to be derived from previously retrieved data, the first client prevents the request from being sent out on the fabric on the data path to memory subsystem. This helps to reduce memory bandwidth consumption and allows the fabric and the memory subsystem to stay in a low-power state for longer periods of time.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas James Gibney
  • Patent number: 10884477
    Abstract: The described embodiments include a computing device with a plurality of clients and a shared resource for processing job items. During operation, a given client of the plurality of clients stores first job items in a queue for the given client. When the queue for the given client meets one or more conditions, the given client notifies one or more other clients that the given client is to process job items using the shared resource. The given client then processes the first job items from the queue using the shared resource. Based on being notified, at least one other client that has second job items to be processed using the shared resource, processes the second job items using the shared resource. The given client can transition the shared resource between power states to enable the processing of job items.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: January 5, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Alexander J. Branover, Benjamin Tsien
  • Publication number: 20200409448
    Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
  • Publication number: 20200409762
    Abstract: A method and apparatus for servicing a task in a computer system includes receiving the task and if the task is serviceable without waking the fabric, servicing the task by a first service stage entity. If the task is not serviceable by the first service stage entity, the task is serviced by a first processing unit without waking a second processing unit. If the task is not serviceable by the first processing unit, the task is serviced by the second processing unit.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Elliot H. Mednick, Benjamin Tsien
  • Patent number: 10861504
    Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 8, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
  • Patent number: 10775874
    Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 15, 2020
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
  • Patent number: 10747298
    Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sridhar V. Gada, Alexander J. Branover
  • Publication number: 20200226081
    Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Vydhyanathan Kalyanasundharam, Philip Ng, Alexander J. Branover, Kevin M. Lepak
  • Patent number: 10712800
    Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 14, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Benjamin Tsien, Alexander J. Branover, Ming L. So, Philip Ng, Xiao Gang Zheng, Felix Ho, Joseph Scanlon, Christopher T. Weaver, Xiaojie He, Carl Kittredge Wakeland
  • Publication number: 20200166985
    Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.
    Type: Application
    Filed: December 5, 2018
    Publication date: May 28, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou