Patents by Inventor Alexander J. Eglit
Alexander J. Eglit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7623126Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.Type: GrantFiled: June 17, 2003Date of Patent: November 24, 2009Assignee: NVIDIA CorporationInventors: Alexander J. Eglit, Sridhar Kotha, Vlad Bril
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Patent number: 7209133Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.Type: GrantFiled: February 7, 2003Date of Patent: April 24, 2007Assignee: NVIDIA International, Inc.Inventors: Alexander J. Eglit, Sridhar Kotha, Vlad Bril
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Publication number: 20030234801Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.Type: ApplicationFiled: June 17, 2003Publication date: December 25, 2003Inventors: Alexander J. Eglit, Sridhar Kotha, Vlad Bril
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Publication number: 20030227471Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.Type: ApplicationFiled: February 7, 2003Publication date: December 11, 2003Inventors: Alexander J. Eglit, Sridhar Kotha, Vlad Bril
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Patent number: 6542150Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.Type: GrantFiled: June 28, 1996Date of Patent: April 1, 2003Assignee: Cirrus Logic, Inc.Inventors: Sridhar Kotha, Vlad Bril, Alexander J. Eglit
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Patent number: 6320574Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.Type: GrantFiled: May 20, 1998Date of Patent: November 20, 2001Assignee: Genesis Microchip, Corp.Inventor: Alexander J. Eglit
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Patent number: 6067071Abstract: A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.Type: GrantFiled: June 27, 1996Date of Patent: May 23, 2000Assignee: Cirrus Logic, Inc.Inventors: Sridhar Kotha, Vlad Bril, Alexander J. Eglit, Robin Sungsoo Han
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Patent number: 6002446Abstract: An upscaler for upscaling a source image to generate a destination image without requiring large buffers. The aspect ratio (ratio of the length of the source image to that of the width) of the source image need not equal the aspect ratio of the destination image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented using only a line buffer.Type: GrantFiled: November 17, 1997Date of Patent: December 14, 1999Assignee: Paradise Electronics, Inc.Inventor: Alexander J. Eglit
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Patent number: 5896179Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.Type: GrantFiled: March 31, 1995Date of Patent: April 20, 1999Assignee: Cirrus Logic, Inc.Inventor: Alexander J. Eglit
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Patent number: 5796392Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.Type: GrantFiled: February 24, 1997Date of Patent: August 18, 1998Assignee: Paradise Electronics, Inc.Inventor: Alexander J. Eglit
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Patent number: 5739867Abstract: An upscaler for upscaling a source image to generate a destination image without having to maintain the aspect ratio (ratio of the length of the source image to that of the width) of the source image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented only a line buffer for upscaling a source image. Prior systems may require large memories such as frame buffers for achieving similar functionality.Type: GrantFiled: February 24, 1997Date of Patent: April 14, 1998Assignee: Paradise Electronics, Inc.Inventor: Alexander J. Eglit
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Patent number: 5712688Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.Type: GrantFiled: December 3, 1996Date of Patent: January 27, 1998Assignee: Cirrus Logic, Inc.Inventor: Alexander J. Eglit
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Patent number: RE40859Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image.Type: GrantFiled: November 20, 2003Date of Patent: July 21, 2009Assignee: Genesis Microchip (Delaware) Inc.Inventor: Alexander J. Eglit
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Patent number: RE41192Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.Type: GrantFiled: April 21, 2006Date of Patent: April 6, 2010Assignee: Genesis Microchip Inc.Inventor: Alexander J. Eglit
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Patent number: RE42615Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.Type: GrantFiled: November 23, 2009Date of Patent: August 16, 2011Assignee: Genesis Microchip (Delaware) Inc.Inventor: Alexander J. Eglit
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Patent number: RE43573Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.Type: GrantFiled: June 24, 2011Date of Patent: August 14, 2012Assignee: Genesis Microchip (Delaware) Inc.Inventor: Alexander J. Eglit