Abstract: Provided herein are energy storage devices. In some cases, the energy storage devices are capable of being transported on a vehicle and storing a large amount of energy. An energy storage device is provided comprising at least one liquid metal electrode, an energy storage capacity of at least about 1 MWh and a response time less than or equal to about 100 milliseconds (ms).

Abstract: In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

Abstract: In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).

Abstract: A thin GaAs Substrate can be provided with a copper back-metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies. By providing the GaAs Substrate with a copper back-metal layer, the GaAs Substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems and allowing the semiconductor die to be compatible with soft-solder technologies. By enabling the semiconductor die to be packaged in a plastic package substantial cost savings can be achieved.

Abstract: method for making a mount for at least two electronic devices forming a first mounting surface (210) from a material (240), and forming a second mounting surface (220) from the material (240). The first mounting surface (210) is connected to, but spaced from, the second mounting surface (220) by a mounting surface distance (250). The method further comprises reducing the mounting surface distance (250).

Abstract: The disclosures made herein relate to RF power semiconductor devices. In accordance with one embodiment of the disclosures made herein, a RF power plastic semiconductor device comprises a semiconductor (RF) device, a Low Temperature Co-Fired Ceramic (LTCC) impedance matching structure electrically connected to the RF device and a plastic package body formed over the RF device and the impedance matching structure. The LTCC impedance matching structure comprises a metallized layer overlying a major body portion of the impedance matching structure and comprises a passivation layer on the metallized layer. The passivation layer enhances bond strength of a mold compound of the plastic package body to the metallized layer. Portions of the metallized layer are exposed through the passivation layer for enabling electrical interconnects to be formed between the LTCC impedance matching structure and the RF device.

Abstract: The disclosures made herein relate to RF power semiconductor devices. In accordance with one embodiment of the disclosures made herein, a RF power plastic semiconductor device comprises a semiconductor (RF) device, a Low Temperature Co-Fired Ceramic (LTCC) impedance matching structure electrically connected to the RF device and a plastic package body formed over the RF device and the impedance matching structure. The LTCC impedance matching structure comprises a metallized layer overlying a major body portion of the impedance matching structure and comprises a passivation layer on the metallized layer. The passivation layer enhances bond strength of a mold compound of the plastic package body to the metallized layer. Portions of the metallized layer are exposed through the passivation layer for enabling electrical interconnects to be formed between the LTCC impedance matching structure and the RF device.

Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).

Abstract: A mount, packaged device, and method of making the same are provided. In one embodiment, a method for making a mount for at least two electronic devices comprises forming a first mounting surface (210) from a material (240), and forming a second mounting surface (220) from the material (240). The first mounting surface (210) is connected to, but spaced from, the second mounting surface (220) by a mounting surface distance (250). The method further comprises reducing the mounting surface distance (250).

Abstract: An electronic component includes a semiconductor substrate (101, 301, 401), an electrically conductive layer (102, 103, 302, 303, 402, 403) supported by the semiconductor substrate (101, 301, 401), and a lead (110, 120, 210, 310, 410, 420) having an electrical coupling portion (112, 122, 212, 312, 412, 422) coupled to and supported by the electrically conductive layer (102, 103, 302, 303, 402, 403) wherein the electrical coupling portion (112, 122, 212, 312, 412, 422) has at least one notch (115, 215, 315) adjacent to the electrically conductive layer (102, 103, 302, 303, 402, 403).

Abstract: A package (10) has outermost surfaces (12, 13, 14, 16) that form a polygon shape. The body (11) of the package (10) has axial symmetry about an axis (21). A lead (22) exits the package along the axis (21).

Abstract: An optoelectronic device is fabricated by casting a transparent polymeric body surrounding an electronic component. A reflective layer is formed over the polymeric body. The reflective layer acts as a mirror to reflect light emitted by one electronic component to another electronic component which receives the light. By casting the polymeric body, a consistent and defined shape for optical transmission is provided for forming the shape of the reflective layer.

Abstract: A duo-cavity multigang pot molding assembly (10) for encapsulating semiconductor devices having an annular cavity (11) to form a molded carrier ring and an inner cavity (12) adapted to receive the item to be encapsulated. An outer mold pot (16) provides encapsulating material for the annular cavity (11) whereas a separate mold pot (17) provides encapsulating material for the inner cavity (12). Encapsulating material for the mold pots (16, 17) may be the same or in a preferred embodiment, different. Molding apparatus (10) promotes improved process control by delivering encapsulating material with a lower and more uniform viscosity to both the annular cavity (11) and the inner cavity (12). Further, use of separate mold pots (16, 17) allows cost savings because a less expensive encapsulating material may be used for molding the molded carrier ring since a high purity encapsulating material is not needed.

Abstract: A clean burning high temperature flame is used to vaporize contaminants from a lead frame's surface, and also vaporize contaminants up to a shallow depth into the lead frame.

Abstract: A method by which leads of a semiconductor component are bent into their final shape using a roll forming process to bend the leads into the desired shape before separation of the individual components. The roll forming process achieves a final form by passing a lead frame holding a plurality of the semiconductor components through a series of form rollers which progressively bend the leads into the final shape. The method can be designed to cut the components free from the lead frame as a final step, minimizing the individual handling of the miniaturized components.