Patents by Inventor Alexander J. Franz

Alexander J. Franz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tool and method to graphically correlate process and test data with specific chips on a wafer
    Patent number: 8234597
    Abstract: A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Flemming, Alexander J. Franz, Tyler D. Kieft, Raghav Kohli, Karl V. Swanke, Matthew S. Turnbull, Matthew Walker
  • TOOL AND METHOD TO GRAPHICALLY CORRELATE PROCESS AND TEST DATA WITH SPECIFIC CHIPS ON A WAFER
    Publication number: 20090183133
    Abstract: A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Inventors: Mark J. Flemming, Alexander J. Franz, Tyler D. Kieft, Raghav Kohli, Karl V. Swanke, Matthew S. Turnbull, Matthew Walker