Patents by Inventor Alexander J. Honcharik

Alexander J. Honcharik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mechanism handling race conditions in FRC-enabled processors
    Patent number: 7194671
    Abstract: An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Steven J. Tu, Alexander J. Honcharik, Hang T. Nguyen, Sujat Jamil, Quinn W. Merrell
  • On-die mechanism for high-reliability processor
    Patent number: 7055060
    Abstract: A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventors: Hang T. Nguyen, Steven J. Tu, Alexander J. Honcharik, Sujat Jamil
  • On-die mechanism for high-reliability processor
    Publication number: 20040123201
    Abstract: A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Hang T. Nguyen, Steven J. Tu, Alexander J. Honcharik, Sujat Jamil
  • Mechanism handling race conditions in FRC-enabled processors
    Publication number: 20030126142
    Abstract: An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Steven J. Tu, Alexander J. Honcharik, Hang T. Nguyen, Sujat Jamil, Quinn W. Merrell