Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.

Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.

Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.

Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.