Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.

Abstract: A simulation application can be executed by a computer system to develop thermal maps for an electronic architectural design. The simulation application can simulate the electronic architectural design over time. The simulation application can capture electronic signals from the electronic architectural design as the electronic architectural design is being simulated over time. The simulation application can determine power consumptions of the electronic architectural design over time from the electronic signals. The simulation application can derive temperatures of the electronic architectural design over time from the power consumptions. The simulation application can map the temperatures onto an electronic circuit design real estate of the electronic architectural design to develop the thermal maps over time.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.

Abstract: A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.

Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.