Abstract: A digital display unit receiving a display signal with image encoded at high origin frequencies (e.g., dot clock). A display signal interface samples the display signal during source display time to generate pixel data elements representative of the images encoded in the display signal. The signal is sampled at a sampling frequency equal to origin frequency. The pixel data elements are stored in a buffer at the sampling frequency and retrieved at a slower frequency. Display signals are generated for each horizontal scan line of a digital display screen during a destination display time at this slower frequency. The destination display time is designed to be longer than the source display time, which enables the display signals to be generated from all pixel data elements. The destination display time is longer than the source display time because digital display units do not require the long non-display times present in the display signals.

Abstract: A digital display unit which accurately determines a graphics source mode using which an analog display signal has been generated. Accurate determination of the source mode enables images encoded in the received display signal to be reproduced properly on a digital display screen. Some of the display signal parameters are measured by examining the display signal. The measured parameters are compared with corresponding stored parameters for each stored mode. A match of parameters is deemed to exist if the compared values are within an associated tolerance level. A source mode matching with all matching parameter is selected to process a display signal. The tolerance level is adaptively varied to select a suitable source mode.

Abstract: A graphics controller circuit in a computer system for generating display signals to a television. The graphics controller circuit may downscale a display image to generate a downscaled image. While downscaling, the graphics controller circuit may generate each horizontal line of a downscaled image from a different number of horizontal lines of a display image. In addition, the graphics controller circuit uses clock signals with different frequencies so as to generate each horizontal line of the downscaled image in the same amount of time. The clock frequencies are designed to generate downscaled image horizontal lines at an input rate required for a television. In effect, the graphics controller circuit may avoid dropping display image horizontal lines while downscaling, and also reduce flicker while displaying the downscaled image on a television.

Abstract: A digital display unit including an analog to digital converter (ADC). When the optimal sampling frequency for sampling an analog display signal is greater than the maximum sampling frequency of the ADC, the analog display signal is sampled using 2:1' interleaved sampling. A smaller image represented by the sampled values is then upscaled prior to being displayed. Such upscaling compensates for the decreased number of samples that would be generated by sampling at lower sampling frequency during 2:1 interleaved sampling.

Abstract: A digital display unit for enabling a user to conveniently select a desired monitor mode to process a display signal. A monitor mode is generally selected by measuring some display signal parameters. If multiple source modes share the same display signal values, all the corresponding monitor modes are stored associated with these common display signal parameter values. The user is provided a convenient interface (such as pushing a button or using a menu provided with an on-screen-display) to cause the display monitor to change the monitor mode. The next monitor mode is again among those associated with the measured display signal parameter values. Accordingly, all the monitor modes associated with the measured display signal parameters can be tried using the interface until a satisfactory display is obtained on the display unit.

Abstract: A computer system in which the signal parameters of an analog display signal received by a display unit can be determined automatically. A test data having a predetermined format is sent to a display unit. The test data is encoded to enable display unit to measure display signal parameters such as the timing signals (e.g., start position of each horizontal line) accurately. The test data also includes black and white points, which enable the display unit to measure the voltage levels used to represent black and white signals. Display unit can accordingly adjust the manner in which individual points on a display screen are actuated so that the full scale of brightness levels on individual points can be utilized. CRC-based techniques are used to indicate to the display unit the presence of the test data as the same communication path is used to send test data and display data.

Abstract: A display controller to upscale a source video image for display on a display unit of a computer system. An encoder circuit stores in a local memory pixel data of previous scan lines required for interpolation in a compressed format using differential pulse code modulation (DPCM) scheme. As a part of the DPCM scheme, encoder generates a predicted value for each source video pixel data as a function of at least one prior pixel data value in the scan line. However, when a slope over load condition is encountered, the decoder circuit changes the predicted value for a subsequent pixel data value to a different value, which may enable the graphics controller circuit to avoid a slope overload condition as to subsequent pixel data values. A decoder circuit decompresses the pixel data into original format prior to sending to an interpolator.

Abstract: A display unit which can determine the frequency (original frequency) used by a graphics source for generating an analog signal. A sequence of test patterns are generated according to a predetermined convention. The sequence of test patterns are encoded in an analog display signal in a graphics source and transmitted to a digital display unit. The digital display unit samples the analog display signal to generate a sequence of sampled values. The digital display unit determines whether the sampled values equal one of the sequence of test patterns based on the predetermined convention. The digital display unit varies (changes) the sampling frequency until the sampled values equal one of the sequence of test patterns. The sampling frequency equals the original frequency when the sampled values equal the sequence of test patterns. In one embodiment, zeros and ones are used in alternate positions of each horizontal line.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.

Abstract: A display controller to upscale a source video image for display on a display unit of a computer system. An encoder circuit in the display controller circuit stores in a local memory pixel data of previous scan lines required for interpolation in a compressed format using differential pulse code modulation (DPCM) scheme. Encoder circuit avoids a slope overload condition by generating compressed data for a first pixel of each scan line by using the first pixel itself as a reference. Encoder circuit generates compressed data for other pixels by using at least one prior pixel in the corresponding scan line. A decoder circuit decompresses the pixel data into original format prior to sending to an interpolator. The interpolator receives a present scan line and the decompressed data of previous scan lines, and interpolates the received pixels to generate additional pixels required for upscaling the source video image.

Abstract: An arrangement and method for adjusting the brightness of an image signal having digital pixel values to produce brightness adjusted output pixel values is provided with an adder and lower and upper clamp circuits. The adder adds a brightness value to the digital pixel values of the image signal to produce adjusted pixel values and a carry-out signal. The lower clamp circuit clamps the adjusted pixel values to a lowest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values below the lowest output pixel value. The upper clamp circuit clamps the adjusted pixel values to a highest output pixel value when the carry-out signal and the brightness value indicate that addition of the brightness value to the digital pixel values produces adjusted pixel values above the highest output pixel value.

Abstract: An adaptive dithering apparatus analyzes an input video signal as a function of available primary shades and produces a select signal whose value is a function of the desired shade represented by the input video signal and of the available primary shades. A combiner combines the input video signal with a selected one of a plurality of dither signals to generate a dithered input video signal. The one dither signal is selected under the control of the select signal. Finally, an adjustor receives the dithered input video signal, the available shade signal, and the select signal and, under the control of the select signal, adjusts the dithered input video signal to have a value equal to one of the available primary shades. Thus, an input video signal may be dithered with a dither signal that is optimized for dithering an input signal that falls into a particular range of desired shades. That is, a different dither signal may be employed for each possible spacing of adjacent available primary shades.

Abstract: A graphics controller circuit for upscaling source video image to generate an upscaled video image. The graphics controller circuit generates additional pixel data for the upscaled video image by interpolating source video pixel data of a one scan line and an another scan line. However, when source video pixel data of the another scan line may not be available for interpolation, the graphics controller circuit generates additional pixel data from source video pixel data of only the one scan line. Source video pixel data of the another scan line may not be available, for example, as a bus that transfers the pixel data may not have sufficient amount of bandwidth.