Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

Abstract: In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.

Abstract: The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode.

Abstract: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.