Patents by Inventor Alexander Klockmann
Alexander Klockmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260352236Abstract: The approaches proposed here relate to the correction of a 1-bit error by means of a BCH code which can correct at least two bit errors, wherein an i-th bit is corrected if the following condition is satisfied: a first syndrome component of an error syndrome in combination with a first element of a Galois field satisfies a first predetermined condition and a second component of the error syndrome in combination with a second element of the Galois field satisfies a second predetermined condition, wherein the second element of the Galois field is determined by the first element of the Galois field.Type: ApplicationFiled: April 27, 2026Publication date: November 5, 2026Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Patent number: 12783351Abstract: A solution for correcting errors is proposed, wherein a bit group of n memory cells is read and n states are determined therefrom, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2. Furthermore, for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, the previously read n-bit code word of the k1-out-of-n code is used to determine possible erroneous bits in the read non-code word. Possible code words of the k2-out-of-n code are determined for the non-code word based on the possible erroneous bits, and error correction is carried out using an external error code based on the possible code words.Type: GrantFiled: October 9, 2024Date of Patent: November 3, 2026Assignee: Infineon Technologies AGInventors: Thomas Kern, Alexander Klockmann, Michael Goessel, George Alkhoury
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Publication number: 20260099406Abstract: A solution for correcting errors is proposed, wherein a bit group of n memory cells is read and n states are determined therefrom, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2. Furthermore, for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, the previously read n-bit code word of the k1-out-of-n code is used to determine possible erroneous bits in the read non-code word. Possible code words of the k2-out-of-n code are determined for the non-code word based on the possible erroneous bits, and error correction is carried out using an external error code based on the possible code words.Type: ApplicationFiled: October 9, 2024Publication date: April 9, 2026Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel, George Alkhoury
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Publication number: 20260051904Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) the second byte series is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) the byte of the second byte sequence is impermissible, and (iii) at least one error is detected if the second byte sequence is impermissible.Type: ApplicationFiled: October 27, 2025Publication date: February 19, 2026Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Publication number: 20260039315Abstract: The approaches proposed here relate to error processing by means of at least two error processing branches. Each of the error processing branches is configured (i) to process a data word, wherein the data words of the error processing branches differ in at least one bit, and (ii) to provide a processed data word to a decision unit. The decision unit is configured to select one of the processed data words or to perform a predetermined action if an uncorrectable error has been detected.Type: ApplicationFiled: July 23, 2025Publication date: February 5, 2026Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Patent number: 12483276Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.Type: GrantFiled: January 29, 2024Date of Patent: November 25, 2025Assignee: Infineon Technologies AGInventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Publication number: 20250183920Abstract: An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.Type: ApplicationFiled: November 25, 2024Publication date: June 5, 2025Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Patent number: 12147303Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.Type: GrantFiled: January 25, 2023Date of Patent: November 19, 2024Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel, Alexander Klockmann, Thomas Rabenalt
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Publication number: 20240257893Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.Type: ApplicationFiled: January 29, 2024Publication date: August 1, 2024Inventors: Thomas Kern, Alexander Klockmann, Michael Goessel
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Publication number: 20230267039Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.Type: ApplicationFiled: January 25, 2023Publication date: August 24, 2023Inventors: Thomas Kern, Michael Goessel, Alexander Klockmann, Thomas Rabenalt
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Publication number: 20220345157Abstract: A solution for detecting a multibyte error in a code word of a shortened error code is proposed, the shortened error code is a ?-byte-correcting error code, wherein bytes of the code word of the shortened error code determined a first range, the non-correctable multibyte error is detected if at least one of the following conditions is met: (a) at least one error position signal does not lie in the first range; (b) at least one error position signal indicates at least one error but fewer than terrors in the first range and no 1-byte error to (??1)-byte error is present.Type: ApplicationFiled: April 13, 2022Publication date: October 27, 2022Inventors: Thomas Kern, Michael Goessel, Alexander Klockmann, Thomas Rabenalt