Abstract: Particular embodiments described herein provide for a system that can be configured to determine an identification (ID) of a computer processing unit (CPU) using one or more tests and/or measurements, intercept the result of a query from a process to determine the ID of the CPU, replace the result of the query if the result of the query does not match the determined ID of the CPU, and communicate the result of the query that includes the determined ID of the CPU to the process. In an example, the query is a CPUID opcode and the results of the query are intercepted after passing through a hypervisor.

Abstract: Particular embodiments described herein provide for a system that can be configured to determine an identification (ID) of a computer processing unit (CPU) using one or more tests and/or measurements, intercept the result of a query from a process to determine the ID of the CPU, replace the result of the query if the result of the query does not match the determined ID of the CPU, and communicate the result of the query that includes the determined ID of the CPU to the process. In an example, the query is a CPUID opcode and the results of the query are intercepted after passing through a hypervisor.

Abstract: Particular embodiments described herein provide for a system that can be configured to determine an identification (ID) of a computer processing unit (CPU) using one or more tests and/or measurements, intercept the result of a query from a process to determine the ID of the CPU, replace the result of the query if the result of the query does not match the determined ID of the CPU, and communicate the result of the query that includes the determined ID of the CPU to the process. In an example, the query is a CPUID opcode and the results of the query are intercepted after passing through a hypervisor.

Abstract: Particular embodiments described herein provide for a system that can be configured to determine an identification (ID) of a computer processing unit (CPU) using one or more tests and/or measurements, intercept the result of a query from a process to determine the ID of the CPU, replace the result of the query if the result of the query does not match the determined ID of the CPU, and communicate the result of the query that includes the determined ID of the CPU to the process. In an example, the the query is a CPUID opcode and the results of the query are intercepted after passing through a hypervisor.

Abstract: Embodiments of apparatus and methods for virtualized computing are described. In embodiments, an apparatus may include one of more processor cores and a cache coupled to the one or more processor cores. The apparatus may further include a hypervisor operated by the one or more processor cores to manage operation of virtual machines on the apparatus, including selecting a part of the cache to store selected data or code of the hypervisor or one of the virtual machines, and locking the part of the cache to prevent the selected data or code from being evicted from the cache. Other embodiments may be described and/or claimed.

Abstract: Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.

Abstract: Embodiments of apparatus and methods for virtualized computing are described. In embodiments, an apparatus may include one of more processor cores and a cache coupled to the one or more processor cores. The apparatus may further include a hypervisor operated by the one or more processor cores to manage operation of virtual machines on the apparatus, including selecting a part of the cache to store selected data or code of the hypervisor or one of the virtual machines, and locking the part of the cache to prevent the selected data or code from being evicted from the cache. Other embodiments may be described and/or claimed.

Abstract: Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.