Patents by Inventor Alexander Kushnarenko
Alexander Kushnarenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230268010Abstract: In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.Type: ApplicationFiled: June 6, 2022Publication date: August 24, 2023Inventors: Yoram Betser, Alexander Kushnarenko
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Publication number: 20230119194Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.Type: ApplicationFiled: January 28, 2022Publication date: April 20, 2023Applicant: Infineon Technologies LLCInventors: Shivananda Shetty, Yoram Betser, Pawan Singh, Stefano Amato, Alexander Kushnarenko
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Patent number: 10304545Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: GrantFiled: June 1, 2018Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 10305461Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: GrantFiled: June 22, 2017Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Alexander Kushnarenko, Yoram Betser
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Publication number: 20190035477Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: ApplicationFiled: June 1, 2018Publication date: January 31, 2019Applicant: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 9991001Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: GrantFiled: May 22, 2014Date of Patent: June 5, 2018Assignee: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Publication number: 20180131358Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: ApplicationFiled: June 22, 2017Publication date: May 10, 2018Inventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 9892763Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.Type: GrantFiled: November 2, 2015Date of Patent: February 13, 2018Assignee: Cypress Semiconductor CorporationInventor: Alexander Kushnarenko
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Patent number: 9543017Abstract: A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.Type: GrantFiled: March 18, 2012Date of Patent: January 10, 2017Assignee: Cypress Semiconductors Ltd.Inventors: Ilan Bloom, Alexander Kushnarenko
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Publication number: 20160232948Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.Type: ApplicationFiled: November 2, 2015Publication date: August 11, 2016Inventor: Alexander Kushnarenko
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Publication number: 20150341023Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Spansion LLCInventors: Alexander Kushnarenko, Yoram Betser
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Publication number: 20150340098Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Spansion LLCInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 9177617Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.Type: GrantFiled: October 8, 2013Date of Patent: November 3, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Alexander Kushnarenko
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Publication number: 20150098290Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Spansion LLCInventor: Alexander Kushnarenko
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Patent number: 8995201Abstract: Disclose is a non-volatile memory (NVM) cell sensing circuit. The sensing circuit may include a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell. Conditioning may include adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase. The conditioning circuit segment may also be adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase. Adjusting a charge density within the NVM cell sense-side-line may include inducing current in the sense-side-line in a direction opposite to the sensing current.Type: GrantFiled: November 7, 2013Date of Patent: March 31, 2015Assignee: Spansion LLCInventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 8760930Abstract: A source-sensing configuration for non-volatile memory devices to simultaneously read 2 bits in two different memory cells sharing a same word line is disclosed. In a first cell arrangement, a drain of a first read cell is biased and its source and that of two adjacent cells in a direction towards the second read cell are connected through source bit lines to a source sense amplifier. In a second cell arrangement, the drain of the second read cell is biased and its source and that of its two adjacent cells in a direction towards the first read cell are connected through source bit lines to a source sense amplifier. A memory cell acts as a cell pipe and joins together the first and second cell arrangements. Driving all six source bit lines simultaneously allows the 2 bits to be simultaneously read while maintaining currents due to pipe effect substantially minimized.Type: GrantFiled: February 18, 2013Date of Patent: June 24, 2014Assignee: Spansion LLC.Inventors: Alexander Kushnarenko, Yoram Betser
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Publication number: 20130242669Abstract: A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.Type: ApplicationFiled: March 18, 2012Publication date: September 19, 2013Applicant: SPANSION ISRAEL LTDInventors: Ilan BLOOM, Alexander KUSHNARENKO
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Patent number: 8339102Abstract: A load adjustment circuit and a method for adjusting a load are provided. The circuit may include a power source to supply power to a load, and a control unit to control a property of the load. The control unit may be adapted to adjust a property of the load based on a signal received from the power source. The method may include supplying power to a load and adjusting a property of the load to decrease the power supplied to the load if the power supplied to the load is greater than a maximum threshold.Type: GrantFiled: November 15, 2004Date of Patent: December 25, 2012Assignee: Spansion Israel LtdInventors: Alexander Kushnarenko, Ifat Nitzan
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Patent number: 8253452Abstract: The present invention is a circuit and method for providing a reference voltage and/or one or more circuit/circuit-block enabling signals for an IC. As the voltage level on a power supply line ramps upward towards or above a nominal operating voltage, a first threshold voltage detector circuit segment may be activated and may begin to generate a bandgap reset signal once the voltage level of the power supply reaches a first threshold voltage level. The bandgap reset signal may trigger the power-up and operation of a bandgap reference circuit segment, and according to further embodiments of the present invention, a second threshold voltage detector circuit segment, which second threshold voltage detector circuit segment may be matched with the first voltage detector circuit, may generate a voltage reset signal indicating that the bandgap reference source is powering-up. Once the supply voltage reaches a third threshold reference voltage, the first detector may disable the bandgap reset.Type: GrantFiled: February 21, 2006Date of Patent: August 28, 2012Assignee: Spansion Israel LtdInventor: Alexander Kushnarenko
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Patent number: 7864606Abstract: A circuit block access module (ICAM) residing on an integrated circuit and adapted to access a circuit block on the integrated circuit, the module comprising control logic adapted to extract data from a serial data line into two or more parallel data lines, wherein at least one of the parallel data lines is associated with a circuit block address line; and the control logic is further adapted to override or bypass at least a portion of a primary control circuit of said integrated circuit.Type: GrantFiled: September 18, 2008Date of Patent: January 4, 2011Assignee: Spansion Israel LtdInventor: Alexander Kushnarenko