Patents by Inventor Alexander L. Martin
Alexander L. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962943Abstract: Camera head apparatus, systems, and methods for providing wide angle/panoramic images and/or video of the interior of pipes or other cavities using multiple imaging and illumination modules are disclosed.Type: GrantFiled: October 10, 2022Date of Patent: April 16, 2024Assignee: SeeScan, Inc.Inventors: Mark S. Olsson, Alexander L. Warren, Nicholas A. Smith, Michael J. Martin, Scott A. Powell
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Patent number: 11588044Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.Type: GrantFiled: December 2, 2020Date of Patent: February 21, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Mankyu Yang, Richard F. Taylor, III, Jagar Singh, Alexander L. Martin
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Patent number: 11575029Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.Type: GrantFiled: May 19, 2021Date of Patent: February 7, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Richard F. Taylor, III, Mankyu Yang, Alexander L. Martin, Judson R. Holt, Jagar Singh
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Publication number: 20230032080Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander M. Derrickson, Mankyu Yang, Judson R. Holt, Jagar Singh, Alexander L. Martin, Richard F. Taylor, III
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Publication number: 20220376093Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander M. Derrickson, Richard F. Taylor, III, Mankyu Yang, Alexander L. Martin, Judson R. Holt, Jagar Singh
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Patent number: 11500198Abstract: Disclosed are a system, method, software tool, etc. for generating a layout indicating the paths for balanced optical waveguides (WGs) of a WG bus. A grid is used to route paths, which extend between corresponding first and second input/output nodes, respectively, and which are within boundaries of a defined area. The paths are automatically rerouted to balance for length and number of bends without overly increasing the lengths of or number of bends in those paths and further without moving the input/output nodes or falling outside the established boundaries. Automatic rerouting of the paths is performed iteratively based on results of various intersection operations related to different path-specific sets of points on the grid to determine when and where to insert additional linear segments and bends into the paths. Then, a layout indicating the balanced paths is generated. Also disclosed is a WG bus structure with balanced optical WGs.Type: GrantFiled: January 12, 2021Date of Patent: November 15, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Won Suk Lee, Thomas G. Weeks, III, Michal Rakowski, Yusheng Bian, Roderick A. Augur, Alexander L. Martin, Petar I. Todorov
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Publication number: 20220221714Abstract: Disclosed are a system, method, software tool, etc. for generating a layout indicating the paths for balanced optical waveguides (WGs) of a WG bus. A grid is used to route paths, which extend between corresponding first and second input/output nodes, respectively, and which are within boundaries of a defined area. The paths are automatically rerouted to balance for length and number of bends without overly increasing the lengths of or number of bends in those paths and further without moving the input/output nodes or falling outside the established boundaries. Automatic rerouting of the paths is performed iteratively based on results of various intersection operations related to different path-specific sets of points on the grid to determine when and where to insert additional linear segments and bends into the paths. Then, a layout indicating the balanced paths is generated. Also disclosed is a WG bus structure with balanced optical WGs.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Won Suk Lee, Thomas G. Weeks, III, Michal Rakowski, Yusheng Bian, Roderick A. Augur, Alexander L. Martin, Petar I. Todorov
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Publication number: 20220173230Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Inventors: Alexander M. Derrickson, Mankyu Yang, Richard F. Taylor, III, Jagar Singh, Alexander L. Martin
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Patent number: 11152496Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.Type: GrantFiled: January 30, 2020Date of Patent: October 19, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Jagar Singh, Alexander L. Martin, Alexander M. Derrickson
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Publication number: 20210242335Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Jagar Singh, Alexander L. Martin, Alexander M. Derrickson
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Patent number: 11011303Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.Type: GrantFiled: August 21, 2018Date of Patent: May 18, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Tung-Hsing Lee, Roderick A Augur, Siva R K Dangeti, Alexander L. Martin, Anvitha Shampur
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Publication number: 20200066438Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Tung-Hsing Lee, Roderick A Augur, Siva R K Dangeti, Alexander L. Martin, Anvitha Shampur
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Patent number: 8039366Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.Type: GrantFiled: February 19, 2009Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Karen L. Holloway, Holly LaFerrara, Alexander L. Martin, Martin E. Powell, Timothy J. Wiltshire, Roger J. Yerdon
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Publication number: 20100207284Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Karen L. Holloway, Holly LaFerrara, Alexander L. Martin, Martin E. Powell, Timothy J. Wiltshire, Roger J. Yerdon
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Patent number: 7700946Abstract: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.Type: GrantFiled: March 27, 2008Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Alexander L. Martin, Eric P. Solecky
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Patent number: 7645620Abstract: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.Type: GrantFiled: October 11, 2005Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Alexander L. Martin, Eric P. Solecky
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Publication number: 20080173869Abstract: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander L. Martin, Eric P. Solecky