Abstract: A circuit configuration includes a symmetrically constructed sample and hold amplifier. A first switchable level shifter has an input in the form of a first signal input terminal for receiving a given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. A second switchable level shifter has an input in the form of a second signal input terminal for receiving a signal complementary to the given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. The input and output signals of each of the switchable level shifters having a different constant direct voltage difference as a function of the switching state of the level shifters.

Abstract: A sample and hold circuit configuration for differential signals with reduced holding capacity includes an amplifier in which the same current ratios prevail in the collector circuit and in the emitter circuit. The base currents are discharged through additional transistors and therefore the same currents flow and equal voltage ratios prevail in the collector and emitter resistors, and an additional diode is connected in each collector circuit.

Abstract: In a method and device for limiting the starting current of a DC converter, at least one buffer capacitor is initially charged through a load resistor. The current going through the load resistor is measured with a monitor. The monitor switches on a DC converter and bridges the load resistor once a switching threshold is reached. A predetermined minimum current is used as the switching threshold.

Abstract: A circuit arrangement for level conversion of ECL-logic levels to TTL-logic levels, having an emitter-coupled current switch with an input addressable by ECL-logic levels, and a TTL-logic output stage, includes a voltage-controlled current source having an input addressable by an output of the current switch, and having an output connected to the TTL-logic output stage.

Abstract: A circuit arrangement for level conversion of TTL-logic levels to ECL-logic levels with at least one emitter-coupled current switch having an input addressable by TTL-logic levels and an output from which ECL-logic levels can be taken off, including a first current switch formed of two emitter-coupled npn-transistors (and a second current switch formed of two emitter-coupled pnp-transistors, one of the transistors of the second current switch being arranged as input stage for the first current switch, the second current switch having a switching threshold higher than that of the first current switch.