Patents by Inventor Alexander Marquardt
Alexander Marquardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8516595Abstract: A system and a method for determining the reliability of blacklists is disclosed. Each blacklist comprises IP addresses of supposedly infected computers. The reliability is computed by analyzing whether the blacklist reports or not controlled infections from sandboxed environments and by measuring the elapsed time between reported infections and disinfections. The obtained information is then used in combination with several metrics for determining the trustworthiness of the IP address of a given Internet host that requests an online transaction with the purpose of granting or denying access to a service.Type: GrantFiled: December 28, 2010Date of Patent: August 20, 2013Assignees: Caixa d'Estalvis I Pensions de Barcelona “La Caixa”, Fundacio Barcelona Digital Centre TecnologicInventors: David Oro García, Jesús Luna Garcia, Antonio Felguera Segador, Alexander Marquardt, Marc Vilanova Vilasero
-
Publication number: 20120167210Abstract: A system and a method for determining the reliability of blacklists is disclosed. Each blacklist comprises IP addresses of supposedly infected computers. The reliability is computed by analyzing whether the blacklist reports or not controlled infections from sandboxed environments and by measuring the elapsed time between reported infections and disinfections. The obtained information is then used in combination with several metrics for determining the trustworthiness of the IP address of a given Internet host that requests an online transaction with the purpose of granting or denying access to a service.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Applicants: FUNDACIO BARCELONA DIGITAL CENTRE TECNOLOGIC, CAIXA D'ESTALVIS I PENSIONS DE BARCELONA "LA CAIXA"Inventors: David ORO GARCIA, Jesús Luna Garcia, Antonio Felguera Segador, Alexander Marquardt, Marc Vilanova Vilasero
-
Patent number: 7671626Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: August 29, 2008Date of Patent: March 2, 2010Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
-
Patent number: 7432734Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: May 2, 2007Date of Patent: October 7, 2008Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
-
Publication number: 20070252617Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: ApplicationFiled: May 2, 2007Publication date: November 1, 2007Inventors: David Lewis, Paul Leventis, Andy Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher Lane, ALexander Marquardt, Vikram Santurkar, Vaughn Betz
-
Patent number: 7218133Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: February 2, 2005Date of Patent: May 15, 2007Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Timothy Betz
-
Patent number: 6937064Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: October 24, 2002Date of Patent: August 30, 2005Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
-
Publication number: 20050127944Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Applicant: Altera CorporationInventors: David Lewis, Paul Leventis, Andy Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz