Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.

Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Abstract: Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.

Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to completion of a cache lookup operation initiated in a cache memory in a higher memory level may be reordered ahead of at least one previously received and pending request awaiting communication to the lower memory level. By doing so, the latency associated with the memory read request is reduced when the request results in a cache miss in the higher level memory, and as a result, system performance is improved.

Abstract: A method for dynamic management of Transmission Control Protocol (TCP) reassembly buffers in hardware (e.g., in a TCP/IP offload engine (TOE)). The method comprises: providing a plurality of data blocks and an indirect list; pointing, via entries in the indirect list, to allocated data blocks in the plurality of data blocks that currently store incoming data; if a free data block in the plurality of data blocks is required for the storage of incoming data, allocating the free data block for storing incoming data; and, if an allocated data block in the plurality of data blocks is no longer needed for storing incoming data, deallocating the allocated data block such that the deallocated data block becomes a free data block.

Abstract: Disclosed is a method and circuit for a receiver to receive data from an associated data transmitter. The receiver may include a signaling module adapted to transmit a Ready-To-Receive (“RTR”) signal to the associated transmitter when a number of vacant bits in a data buffer exceeds a delay associated value.

Abstract: A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to completion of a cache lookup operation initiated in a cache memory in a higher memory level may be reordered ahead of at least one previously received and pending request awaiting communication to the lower memory level. By doing so, the latency associated with the memory read request is reduced when the request results in a cache miss in the higher level memory, and as a result, system performance is improved.

Abstract: A processor receives one or more debug commands through a debug port to help debug software being executed by the processor. In response to a first one or more of the debug commands, the processor stops execution of the software, and flushes data from cache memory of the processor to one or more data locations external to the processor. In response to a second one or more of the debug commands, the processor accesses one or more data locations external to the processor, and resumes execution of the software.

Abstract: A method and system for dynamic management of Transmission Control Protocol (TCP) reassembly buffers in hardware (e.g., in a TCP/IP offload engine (TOE)). The method comprises: providing a plurality of data blocks and an indirect list; pointing, via entries in the indirect list, to allocated data blocks in the plurality of data blocks that currently store incoming data; if a free data block in the plurality of data blocks is required for the storage of incoming data, allocating the free data block for storing incoming data; and, if an allocated data block in the plurality of data blocks is no longer needed for storing incoming data, deallocating the allocated data block such that the deallocated data block becomes a free data block.

Abstract: A method for transforming a data octet (8B) including eight bits into a ten-bit code group (10B) including ten bits, the method including deriving an intermediate result from a table having fewer than 500 entries, and performing a logical operation on the intermediate result to generate the ten-bit code group. Related apparatus and methods are also described.