Patents by Inventor Alexander Miretsky
Alexander Miretsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10019380Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.Type: GrantFiled: September 25, 2015Date of Patent: July 10, 2018Assignee: QUALCOMM IncorporatedInventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh
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Patent number: 10007619Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.Type: GrantFiled: September 20, 2015Date of Patent: June 26, 2018Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Alexander Miretsky, Meghal Varia, Kyle John Ernewein, Manokanthan Somasundaram, Muhammad Umar Choudry, Serag Monier Gadelrab
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Patent number: 9836410Abstract: A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.Type: GrantFiled: September 25, 2015Date of Patent: December 5, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Alexander Miretsky
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Patent number: 9824015Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: November 21, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Patent number: 9785559Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Patent number: 9747213Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: August 29, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Publication number: 20170091116Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh
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Publication number: 20160350234Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.Type: ApplicationFiled: September 20, 2015Publication date: December 1, 2016Inventors: Jason Edward PODAIMA, Paul Christopher John WIERCIENSKI, Carlos Javier MOREIRA, Alexander MIRETSKY, Meghal VARIA, Kyle John ERNEWEIN, Manokanthan SOMASUNDARAM, Muhammad Umar CHOUDRY, Serag Monier GADELRAB
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Publication number: 20160350222Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Inventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Publication number: 20160306746Abstract: A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.Type: ApplicationFiled: September 25, 2015Publication date: October 20, 2016Inventors: Jason Edward PODAIMA, Paul Christopher John WIERCIENSKI, Alexander MIRETSKY
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Publication number: 20110093644Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.Type: ApplicationFiled: November 11, 2010Publication date: April 21, 2011Inventors: Warren F. Kruger, Patrick Law, Alexander Miretsky
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Patent number: 7849256Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.Type: GrantFiled: July 11, 2006Date of Patent: December 7, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Warren F. Kruger, Patrick Law, Alexander Miretsky
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Patent number: 7657774Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.Type: GrantFiled: June 16, 2008Date of Patent: February 2, 2010Assignee: LSI Logic CorporationInventors: Eric Hung, Geeta K. Desai, Vijendra Kuroodi, Alexander Miretsky, Mirko Vojnovic
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Patent number: 7409572Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.Type: GrantFiled: December 5, 2003Date of Patent: August 5, 2008Assignee: LSI CorporationInventors: Eric Hung, Geeta K. Desai, Vijendra Kuroodi, Alexander Miretsky, Mirko Vojnovic
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Publication number: 20080016254Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.Type: ApplicationFiled: July 11, 2006Publication date: January 17, 2008Inventors: Warren F. Kruger, Patrick Law, Alexander Miretsky
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Patent number: 6647462Abstract: An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.Type: GrantFiled: June 29, 2000Date of Patent: November 11, 2003Assignee: Motorola, Inc.Inventors: Alexander Miretsky, Vitaly Sukonik, Amit Dor, Rami Natan
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Patent number: 6553487Abstract: A device and method for performing high speed low overhead context switch, and especially in processors that handle multilevel nested tasks. The device handles forward requests and backward requests. The device is coupled to a central processing unit and has plurality of register files and a direct memory access mechanism that allows a processor to respond to a forward request by starting to handle a higher priority task using a first register file while transferring the halted task context from the second register file to a context save area within a memory module. The processor responds to a backward request by using the context that is stored in a first register file, while transferring to the second register file a lower priority task context.Type: GrantFiled: January 7, 2000Date of Patent: April 22, 2003Assignee: Motorola, Inc.Inventors: Vitaly Sukonik, Alexander Miretsky, Amit Dor