Abstract: A final passivation structure for a semiconductor device having conductive lines formed on a surface of the semiconductor device, comprising a planarized layer covering the surface and also covering the conductive lines, and a diffusion barrier covering the planarized layer. Alternately, the planarized layer may partially cover the conductive lines.

Abstract: According to one aspect of the invention, there is provided a method for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having memory cells and redundancy memory cells in at least one memory array and an associated redundancy memory array, respectively. The memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively. The method optionally includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory.

Abstract: A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection includes monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: A simplified crack stop formation compatible with shallow fuse etch processes which are utilized for modern low-cost redundancy designs using upper level metal fuses. A modified last level metallization (LLM) etch according to the invention allows a high-productivity single step bondpad/fuse/crack stop etch. The stack of metal films formed at the edge of the dicing channel is readily removed with a modified LLM etch prior to dicing causing the insulator films covering the dicing channel to be physically separated from the insulators coating the electrically active chip areas. The separation prevents cracks that could propagate through the insulators of the dicing channel in to the active chip.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection comprises monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: A method and apparatus for dicing a semiconductor wafer in which the wafer is bowed or bent by forcing it into contact with a spherical surface having parallel grooves therein and in which an array of parallel wire saws that are in registration with the grooves is forced against the wafer for sawing parallel channels therethrough. A second array of parallel wire saws that are orthogonal to the wires of the first array is provided spaced therefrom for sawing parallel channels through the wafer that are orthogonal to the channels produced by the first array of parallel wire saws.

Abstract: An improved etch behavior is promoted to generate vertical sidewalls for fuse links that will promote reliable and repeatable laser cutting of the fuse links. In one embodiment, dummy structures are added adjacent to fuse links in order to obtain the vertical sidewalls for reliable fuse deletion. The dummy structures form no part of the fuse or circuit structure but, because of the proximity of the dummy structures to the fuse links, vertical sidewalls are promoted in a reactive ion etch which is used to form the fuse array. In another embodiment, the vertical sidewalls of the fuse links are achieved in a damascene process in which grooves are formed in an oxide layer and filled with a metal. These grooves correspond to the fuse links and alternating dummy structures. Once filled, the surface is planarized using a chemical-mechanical process. The dummy structures provide reinforcement for the metallization (metal and dielectric film), maintaining the integrity of the metallization.