Abstract: A multicore processor is provided. In order to select one of the multiple cores in such a multicore processor, an execution time of tasks which are performed multiple times is determined. Based on the determined execution time on the individual cores, an appropriate core for further executions of a task is selected. Additionally, the present disclosure further provides a code generator and code generating method for providing appropriate machine code for the multicore processor.

Abstract: The present application relates to the field of neural networks, in particular Binary Neural Networks (BNN). The application proposes a device and method for regularization of a BNN. The device is configured to obtain binary weights of the BNN, and to change the binary weights of the BNN using a backpropagation method. Thereby, changing the binary weights increases or minimizes decrease of an information entropy of a weight distribution.

Abstract: The present disclosure relates to a multicore processor. In order to select one of the multiple cores in such a multicore processor, an execution time of tasks which are performed multiple times is determined. Based on the determined execution time on the individual cores, an appropriate core for further executions of a task is selected. Additionally, the present disclosure further provides a code generator and code generating method for providing appropriate machine code for a multicore processor.

Abstract: A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: A machine-based method for modifying a parity-check matrix in a manner that controllably and quantifiably raises the corresponding error-floor level and/or rate of miscorrection to make these quantities observable in direct read-channel simulations that can be completed in a relatively short amount of time. In one embodiment, the method is used to compare different turbo-decoding schemes by comparing the read-channel performance characteristics corresponding to a modified matrix, instead of the original parity-check matrix. In another embodiment, the method is used to validate a heuristic error-rate estimation tool. After being validated, the heuristic error-rate estimation tool can advantageously be used to obtain, in a relatively short amount of time, relatively accurate estimates of the error rates corresponding to the original parity-check matrix.

Abstract: A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the latter having been identified based on said codeword/waveform classification. The acceleration is achieved, at least in part, because the relatively highly time-consuming processing steps implemented in the second read-channel simulator are applied to fewer codewords than otherwise required by conventional simulation methods.

Abstract: In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation. The arbitrary noise increases the probability of converging on a trapping set and does not represent any noise introduced by the communications channel. The simulator attempts to decode the noisy signal, and if decoding is unsuccessful, then the simulator increments an error counter corresponding to the selected signal-to-noise ratio. This process is repeated for all possible combinations of signal-to-noise ratio values and codeword patterns to determine the error rate for all of the signal-to-noise ratio values.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: In one embodiment, a heterogeneous multi-processor computer system includes (i) a plurality of dedicated processors (DPs), each DP configured to implement one or more program modules during runtime operations; (ii) two or more control processors (CPs), each CP configured to run scheduling software for controlling the runtime operations by a corresponding subset of DPs; and (iii) one or more buses interconnecting the DPs and CPs. Each CP is configured to vary timing of implementation of the program modules for the corresponding subset of DPs based on resource availability, and each CP is configured to vary timing of data transfers by the corresponding subset of DPs based on resource availability.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors. The system comprising a plurality of processors of two or more different processor types. Machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution. A Source Code Generator (SCG) integrates scheduling information for the selected schedule solution into the scheduling software for a first processor such that the scheduling information is compiled with the scheduling software.