Abstract: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

Abstract: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

Abstract: A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

Abstract: A correcting device (6) with substitute memory words (8) which take on the function of memory words identified as defective in the memory (1) is assigned for correcting the errors of a digital memory (1). Memory access to memory words of the memory (1) identified as defective is for this purpose diverted to corresponding substitute memory words (8). According to the invention the memory (1) has different lines (2, 3) for reading and for writing, wherein when there is write access a value written into a memory word via an input line (2) is read out again and appears on the output line (3) (write-through memory). Each time there is write access to a memory word of the memory (1) the written value is compared with the value output via the output line (3) and if there is incorrect agreement the corresponding memory word is identified as defective.