Abstract: Time-slot interchange (TSI) switches include a data memory having first entries therein that contain serial data received by the switch and a connection memory having second entries therein. When programmed, these second entries contain addresses of a plurality of the first entries in the data memory and switching modes that have been assigned to the plurality of the first entries. A control circuit is also provided to automatically program a block of the second entries in the connection memory with updated switching modes during an efficient burst program mode of operation. An internal bypass feature is also provided to support efficient testing/debugging of downstream devices in a communications path.

Abstract: Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.