Abstract: A rotor assembly includes a substantially cylindrical support structure having at least one first region, and at least one second region. At least one rotor coil is positioned within each first region of the substantially cylindrical support structure. Each rotor coil includes a pair of distal end portions and a convex center portion, and the average mechanical density of the convex center portion is substantially equal to the average mechanical density of the distal end portions. The average mechanical density of the at least one first region is substantially equal to the average mechanical density of the at least one second region.

Abstract: A rotor assembly includes a substantially cylindrical support structure having at least one first region, and at least one second region. At least one rotor coil is positioned within each first region of the substantially cylindrical support structure. Each rotor coil includes a pair of distal end portions and a convex center portion, and the average mechanical density of the convex center portion is substantially equal to the average mechanical density of the distal end portions. The average mechanical density of the at least one first region is substantially equal to the average mechanical density of the at least one second region.

Abstract: A network computer system and method are disclosed that provides access to a large number of concurrent clients without undesirable processor lag and delays. The system prepares client objects in advance of client access requests and can dynamically create new client objects over a distributed system when needed. Buffering is provided to avoid processor interrupts.

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions.

Abstract: Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.

Abstract: An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder alone or the execution unit together with the 3 bit adder depending upon how much the present address must be incremented to obtain the new addresses.

Abstract: A full glove of water-proof material such as rubber includes a thumb, index and long finger having short firm bristles on the exterior, for brushing canine teeth.

Abstract: A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in conjunction with the arithmetic unit to calculate offsets, limits, and linear addresses in a single cycle.