Abstract: In a memory array, dual port capability is achieved by an arrangement of the memory cells such that for each cycle of the memory operation two accesses may be performed. This result is achieved by taking advantage of the bit line precharging interval. A second bit line accessing pair is added to each memory element, and each cycle is split so that when one bit line is in the accessing mode, the other bit line is in the precharging mode. Using this technique the speed of the memory is effectively doubled.

Abstract: A time slot interchanger is disclosed for selecting and buffering digital signals between buses. The arrangement is particularly useful in forming conferences in a distributed digital time division system. In one embodiment, a clock is used to generate time signals corresponding to time slots of the first bus. These signals are sequentially provided to an associative memory and when a match occurs between the provided signal and a priorly stored time slot identity, an enable signal is provided. The enable signal has a time identity with a first bus time slot and a physical identity with a particular second bus time slot. The enable signal is used to gate into a second memory the time slot signal associated with the time identity at the storage location in the second memory corresponding with the particular time slot of the second bus associated with the enable signal. The signal samples are then sequentially removed from the second memory.