Patents by Inventor Alexander Redkin

Alexander Redkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Using Reduced Instruction Set Cores
    Publication number: 20140258685
    Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
    Type: Application
    Filed: December 30, 2011
    Publication date: September 11, 2014
    Inventors: Srihari Makineni, Steven R. King, Alexander Redkin, Joshua B. Fryman, Ravishankar Iyer, Pavel S. Smirnov, Dmitry Gusev, Dmitri Pavlov
  • Configurable Reduced Instruction Set Core
    Publication number: 20140223145
    Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
    Type: Application
    Filed: December 30, 2011
    Publication date: August 7, 2014
    Applicant: Intel Corporation
    Inventors: Srihari Makineni, Steven R. King, Zhen Fang, Alexander Redkin, Ravishankar Iyer, Pavel S. Smirnov, Dmitry Gusev, Dmitri Pavlov, May Wu
  • Encoding to Increase Instruction Set Density
    Publication number: 20140082334
    Abstract: A conventional instruction set architecture such, as the x86 instruction set architecture, may be reencoded to reduce the amount of memory used by the instructions. This may be particularly useful in applications that are memory sized limited, as is the case with microcontrollers. With a reencoded instruction set that is more dense, more functions can be implemented or a smaller memory size may be used. The encoded instructions are then naturally decoded at run time in the predecoder and decoder of the core pipeline.
    Type: Application
    Filed: December 30, 2011
    Publication date: March 20, 2014
    Inventors: Steven R. King, Sergey Kochuguev, Alexander Redkin, Srihari Makineni