Abstract: A power semiconductor module arrangement includes a power semiconductor module, wherein the power semiconductor module includes a substrate for carrying at least one semiconductor body, and a heat-conducting layer arranged on a lower surface of the power semiconductor module, wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink, and wherein the heat-conducting layer consists of a metallic and non-eutectic material that is solid at temperatures below a first threshold temperature, that is viscous at temperatures above the first threshold temperature and below a second threshold temperature, and that is fluid at temperatures above the second threshold temperature.

Abstract: A power electronics device comprises a power electronics carrier includes a non-corrosive metal substrate and a region of electrical isolation material that forms a direct interface with the metal substrate, and a first semiconductor die mounted on the region of electrical isolation material, and a coefficient of thermal expansion of the region of electrical isolation material substantially matches a coefficient of thermal expansion of metal from the metal substrate at the direct interface.

Abstract: The present invention relates to the technical area of the application of plant protection agent. The subjects of the present invention are a device and a method for the automated and precise application of one or more plant protection agents on a target object and for the documentation of the application.

Abstract: An encapsulant is disclosed. In one example, the encapsulant is an electronic package, wherein the encapsulant comprises an electrically insulating matrix material. Stress inhibiting filler particles, having a value of the coefficient of thermal expansion of not more than 6 ppm/K and a value of the Young modulus of not more than 4 GPa, are located in the matrix material.

Abstract: A measurement application device calibration unit, system, and method includes at least one coupling element comprising a first and second connections for coupling the coupling element into a signal measurement path that is coupled to a measurement application device, and a third connection, wherein the coupling element is configured to at least one of couple out a signal from the signal measurement path into the third connection, and couple in a signal from the third connection into the signal measurement path, and a signal processing device that is coupled to the third connection of the coupling element and that is configured to receive a predetermined calibration signal when the coupling element couples out a signal from the signal measurement path into the third connection, and to generate a predetermined known calibration signal when the coupling element couples in a signal from the third connection into the signal measurement path.

Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.

Abstract: A radio frequency testing apparatus with voltage standing wave ratio adjustment for testing a device under test is provided. Said radio frequency testing apparatus comprises an input, an output, a signal source for providing a test signal for the device under test via the output, thereby forming an output signal path, a signal sink for receiving a received signal from the device under test via the input, thereby forming an input signal path, and a tracking generator. In this context, the tracking generator and/or the signal sink is configured to determine a corresponding voltage standing wave ratio at the input and/or at the output. Furthermore, the signal source is configured to pre-equalize the test signal on the basis of the corresponding voltage standing wave ratio at the output and/or the input. In addition to this or as an alternative, the signal sink is configured to post-correct the received signal on the basis of the corresponding voltage standing wave ratio at the input and/or the output.

Abstract: A method of providing signal level performance information with respect to an electronic component is described. The electronic component includes a signal input. An input signal is received at the signal input or immediately upstream of the signal input. At least one power level parameter is determined, wherein the power level parameter is indicative of a power level of the input signal received. A performance indicator is provided, which includes information on a performance of the electronic component in dependence of the at least one power level parameter. A signal level performance information is determined with respect to the electronic component based on the at least one determined power level parameter and based on the performance indicator. Further, a monitoring system is described.

Abstract: A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between ?40° C. to 150° C.

Abstract: A measurement system includes an input port, a signal splitter, first and second signal paths, an analysis circuit, and a control circuit. The input port is configured to receive an input signal to be measured. The signal splitter is configured to split the input signal into a first signal that is forwarded to the first signal path and a second signal that is forwarded to the second signal path. The analysis circuit is connected to the first signal path and the second signal path so as to receive both a first processed signal and a second processed signal. The analysis circuit is configured to a complex-valued product signal from the processed signals average the complex-valued product signal over a predetermined number of samples, and determine an averaged power signal based thereon. The control circuit is configured to directly or indirectly add an offset to the averaged power signal.

Abstract: A phase coherent synthesizer with good phase noise and spurious performance is described. The phase coherent synthesizer includes digital direct synthesizer (DDS) circuitry, frequency multiplier circuitry, an oscillator, and a mixing stage. The digital direct synthesizer (DDS) circuitry has a first output and a second output. The first output is associated with a fine resolution synthesis. The second output is associated with a step synthesis. A second output signal provided via the second output has a higher frequency compared with a first output signal provided via the first output. The frequency multiplier circuitry is connected with the second output. The frequency multiplier circuitry is configured to multiply the second output signal received via the second output, thereby generating a multiplied output signal. The mixing stage has two input ports connected with the frequency multiplier circuitry and the oscillator respectively.

Abstract: A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 ?m, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Abstract: A DBC substrate for power semiconductor devices includes a ceramic workpiece of a non-oxide ceramic having first and second opposing main sides, the ceramic workpiece having a thickness of 10 ?m or more measured between the first and second main sides, a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 ?m or more, and an intermediate layer comprising Al2O3 disposed between the ceramic workpiece and the copper-containing layer.

Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.

Abstract: A semiconductor module includes a first metal layer, a ceramic layer applied on the first metal layer, a second metal layer applied at least in part on the ceramic layer, and a semiconductor die attached on a portion of the second metal layer. A method for fabricating the semiconductor module is also described.

Abstract: A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 ?m, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Abstract: A solderable electronic device includes: a base including one or more of a semiconductor die and a power electronic substrate; a first layer arranged over the base, the first layer including a solid reducing agent; and a solder preform arranged over the first layer. The solid reducing agent is configured to reduce a solder material of the solder preform during a soldering process.

Abstract: A method for fabricating a semiconductor package includes: providing a die carrier; disposing a semiconductor die on the die carrier, the semiconductor die having one or more contact pads on a first main face thereof; applying an encapsulant at least partially to the semiconductor die, the encapsulant embedding at least one electrical connector, the electrical connector being connected with a contact pad or with the die carrier and extending to a main face of the encapsulant; and depositing at least one electrical layer onto the main face of the encapsulant and an exposed end of the at least one electrical connector.

Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.

Abstract: The present disclosure relates to a method for testing a device under test by using a test system. The method comprises the steps of: generating a wideband modulated signal; forwarding the wideband modulated signal to an input of a device under test; separating an electromagnetic wave reflected at the input by the directional element; forwarding the reflected electromagnetic wave to a test and measurement instrument; processing a reference signal associated with the wideband modulated signal; and determining a channel response by taking the reference signal and at least one scattering parameter of the device under test into account, wherein the scattering parameter depends on the reflected electromagnetic wave. Further, the present disclosure relates to a test system.