Patents by Inventor Alexander Rucker

Alexander Rucker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of improving L1 icache performance with large programs
    Patent number: 12675415
    Abstract: The hit rate of a L1 icache when operating with large programs is substantially improved by reserving a section of the L1 icache for regular instructions and a section for non-instruction information. Instructions are prefetched for storage in the instruction section of the L1 icache based on information in the non-instruction section of the L1 icache.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 7, 2026
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Edward McLellan, Alexander Rucker, Shay Gal-On, Srilatha Manne
  • Method of cache prefetching that increases the hit rate of a next faster cache
    Patent number: 11645209
    Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 9, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
  • METHOD OF CACHE PREFETCHING THAT INCREASES THE HIT RATE OF A NEXT FASTER CACHE
    Publication number: 20210365378
    Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
  • Method of cache prefetching that increases the hit rate of a next faster cache
    Patent number: 11080195
    Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 3, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker
  • METHOD OF IMPROVING L1 ICACHE PERFORMANCE WITH LARGE PROGRAMS
    Publication number: 20210081323
    Abstract: The hit rate of a L1 icache when operating with large programs is substantially improved by reserving a section of the L1 icache for regular instructions and a section for non-instruction information. Instructions are prefetched for storage in the instruction section of the L1 icache based on information in the non-instruction section of the L1 icache.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Edward MCLELLAN, Alexander RUCKER, Shay GAL-ON, Srilatha MANNE
  • METHOD OF CACHE PREFETCHING THAT INCREASES THE HIT RATE OF A NEXT FASTER CACHE
    Publication number: 20210073132
    Abstract: The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: Shay Gal-On, Srilatha Manne, Edward McLellan, Alexander Rucker