Abstract: Various technologies described herein pertain to mitigating motion misalignment of a time-of-flight sensor system and/or generating transverse velocity estimate data utilizing the time-of-flight sensor system. A stream of frames outputted by a sensor of the time-of-flight sensor system is received. A pair of non-adjacent frames in the stream of frames is identified. Computed optical flow data is calculated based on the pair of non-adjacent frames in the stream of frames. Estimated optical flow data for at least one differing frame can be generated based on the computed optical flow data, and the at least one differing frame can be realigned based on the estimated optical flow data. Moreover, transverse velocity estimate data for an object can be generated based on the computed optical flow data.

Abstract: Various technologies described herein pertain to mitigating motion misalignment of a time-of-flight sensor system and/or generating transverse velocity estimate data utilizing the time-of-flight sensor system. A stream of frames outputted by a sensor of the time-of-flight sensor system is received. A pair of non-adjacent frames in the stream of frames is identified. Computed optical flow data is calculated based on the pair of non-adjacent frames in the stream of frames. Estimated optical flow data for at least one differing frame can be generated based on the computed optical flow data, and the at least one differing frame can be realigned based on the estimated optical flow data. Moreover, transverse velocity estimate data for an object can be generated based on the computed optical flow data.

Abstract: A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Abstract: A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Abstract: A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Abstract: A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.

Abstract: Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

Abstract: Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

Abstract: A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.

Abstract: A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value.

Abstract: A fuel cell system (and a method for operating it) includes at least one fuel cell with an anode space and a cathode space, a first medium supply line for supplying a first medium to the anode space, a first medium outlet line for removing an outgoing anode stream from the anode space, a second medium supply line for supplying a second medium to the cathode space, a second medium outlet line for removing an outgoing cathode stream from the cathode space, and a heater device which is arranged downstream of the at least one fuel cell and is acted on by outgoing fuel cell stream. A starting material is evaporated in an evaporator.