Abstract: Embodiments of the present invention provide a voltage protection apparatus (130, 160, 205, 630, 730), comprising an input (165, 210, 610, 710) to receive an input voltage provided to a processor (120), an output (190, 260, 680, 760) to output a throttle signal to the processor (120), a filter circuit (180, 240, 640, 660, 740) to filter the input voltage provided to the processor (120) to provide a filtered input voltage, and a first circuit (170, 230, 630, 650, 73) to compare the filtered input voltage to a first threshold voltage (175, 235, 635, 645, 735) and to cause the output (190, 260, 680, 760) to provide the throttle signal to the processor (120) indicative of the filtered input voltage dropping below the first threshold voltage.

Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Techniques and mechanisms for supplementing power delivery with a battery. In an embodiment, a voltage is provided at a first node with the battery to power a load circuit. A charger is coupled between the first node and a second node, wherein a capacitor is coupled to provide charge to the charger via the second node. In response to detecting a transition of the voltage below a threshold voltage level, controller logic operates switch circuitry of the charger to provide charge from the capacitor. Such operation maintains the voltage in a range of voltage levels which are each above a minimum voltage level required by the load. At least a portion of the range is below the threshold voltage level. In some embodiments, another voltage at the second node provides a basis for generating a control signal to throttle an operation of the load circuit.

Abstract: A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Systems, apparatuses and methods may provide for technology that supplements a battery coupled to a processor configuration with stored energy from a charger input, wherein the battery is supplemented with the stored energy in response to an increased power demand on the battery. The technology may also initiate one or more throttle operations in the processor configuration if the increased power demand does not end before the stored energy is depleted. If the increased power demand ends before the stored energy is depleted, the one or more throttle operations may be bypassed. The increased power demand may correspond to a system voltage being below a voltage threshold, a battery current being above a current threshold, and so forth.

Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Abstract: Techniques and mechanisms for supplementing power delivery with a battery. In an embodiment, a voltage is provided at a first node with the battery to power a load circuit. A charger is coupled between the first node and a second node, wherein a capacitor is coupled to provide charge to the charger via the second node. In response to detecting a transition of the voltage below a threshold voltage level, controller logic operates switch circuitry of the charger to provide charge from the capacitor. Such operation maintains the voltage in a range of voltage levels which are each above a minimum voltage level required by the load. At least a portion of the range is below the threshold voltage level. In some embodiments, another voltage at the second node provides a basis for generating a control signal to throttle an operation of the load circuit.

Abstract: Systems, apparatuses and methods may provide for technology that supplements a battery coupled to a processor configuration with stored energy from a charger input, wherein the battery is supplemented with the stored energy in response to an increased power demand on the battery. The technology may also initiate one or more throttle operations in the processor configuration if the increased power demand does not end before the stored energy is depleted. If the increased power demand ends before the stored energy is depleted, the one or more throttle operations may be bypassed. The increased power demand may correspond to a system voltage being below a voltage threshold, a battery current being above a current threshold, and so forth.

Abstract: An electronic device may include a battery charger and a controller. The battery charger may receive a voltage from an energy source, and may provide an output power. The controller may receive a voltage value of the energy source, may receive a current value from the battery charger or the energy source, may determine a power value based on the received voltage value and the received current value, and may provide at least one control signal to the battery charger to change the output power of the charger.

Abstract: A computing system may include a base portion to receive one or more first batteries, and a tablet portion having one or more electronic components and the tablet portion to receive one or more second batteries. The tablet portion may be configured to be coupled to and detached from the base portion. The computing system may also include circuitry to control a supply of voltage to one or more electronic components of the tablet portion from one or more first batteries at the base portion and from one or more second batteries at the tablet portion.

Abstract: A method and apparatus for adjusting the charge for a battery under a power sharing arrangement is disclosed. In one embodiment, the method comprises determining if power output capacity of an alternating current (AC) adapter is less than or greater than a system power requirement for a system that receives power from the AC adapter and a battery, determining a charge current for charging the battery from the AC adapter, based on a voltage range of the battery, the current charge being less than excess current available from the AC adapter in view of determining that the power output capacity of the AC adapter is greater than the system power requirement, and controlling a battery charger to charge the battery with the charge current by specifying the charge current to the battery charger if the power output capacity of the AC adapter is greater than the system power requirement.

Abstract: Techniques for processing audio data are described. An example of a computing device includes a microphone array to generate audio data and a camera. The computing device is to receive video data from the camera and identify a beam forming target based, at least in part, on the video data. The computing device also includes a beam former to process the audio data to aim a beam of the microphone array at the beam forming target.

Abstract: An apparatus for audio beamforming is composed of a wearable device (100). Wearable device (100) includes a central processing unit (102), motion sensors (116) and microphones (118). Multiple microphones (118) of wearable device (100) are used to create a microphone array that can be beamformed towards the speaker's voice. A method for adjusting beamforming is also provided.

Abstract: An on-package voltage regulation system includes a platform controller hub (PCH), a driver metal-oxide-semiconductor field-effect transistor (DRMOS) control unit, and a plurality of inductors coupled to an output node. The PCH receives a voltage feedback signal corresponding to an output voltage at the output node, and outputs a control signal based on a difference between the voltage feedback signal and a reference voltage. The DRMOS control unit includes a plurality of switch transistors and a DRMOS controller. The switch transistors are coupled to the output node through the plurality of inductors. The DRMOS controller includes logic to determine an output current based on the control signal from the PCH, and to determine a distribution of the output current through the plurality of inductors. Transistor drivers control the switch transistors to share the output current through the plurality of inductors based on the determined output current and distribution.

Abstract: An apparatus for audio beamforming is composed of a wearable device (100). Wearable device (100) includes a central processing unit (102), motion sensors (116) and microphones (118). Multiple microphones Memory Camera (118) of wearable device (100) are used to create a microphone array that can be beamformed towards the speaker's voice. A method for adjusting beam-forming is also provided.

Abstract: A chassis for an electronic device may include a first metal layer to form an inner surface of the chassis, an insulating layer on the first metal layer, and a second metal layer on the insulating layer. The second metal layer may be connected to a ground area of a circuit board to be provided in the chassis.