Patents by Inventor Alexander V. Reshetov

Alexander V. Reshetov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163187
    Abstract: A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: December 25, 2018
    Assignee: Intel Corproation
    Inventors: Alexei Soupikov, Maxim Y. Shevtsov, Alexander V. Reshetov
  • Patent number: 10121276
    Abstract: A method, computer readable medium, and system are disclosed for generating and utilizing infinite resolution texture acceleration data structures. The method for generating an infinite resolution texture acceleration data structure includes the steps of receiving an image; generating an infinite resolution texture acceleration data structure associated with the image that includes a texture map, a curve index map, and a curve data map; and storing the infinite resolution texture acceleration data structure in a memory. The texture map is a two-dimensional array of texels, each texel encoding a color value based on the image. The curve data map encodes parameters for at least one curve segment associated with the image. The curve index map associates each texel in the texture map with zero or more curve segments corresponding with the texel.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: November 6, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Alexander V. Reshetov, David Patrick Luebke
  • Publication number: 20180158227
    Abstract: A method, computer readable medium, and system are disclosed for generating and utilizing infinite resolution texture acceleration data structures. The method for generating an infinite resolution texture acceleration data structure includes the steps of receiving an image; generating an infinite resolution texture acceleration data structure associated with the image that includes a texture map, a curve index map, and a curve data map; and storing the infinite resolution texture acceleration data structure in a memory. The texture map is a two-dimensional array of texels, each texel encoding a color value based on the image. The curve data map encodes parameters for at least one curve segment associated with the image. The curve index map associates each texel in the texture map with zero or more curve segments corresponding with the texel.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 7, 2018
    Inventors: Alexander V. Reshetov, David Patrick Luebke
  • Patent number: 9582858
    Abstract: Anti-aliasing methods and systems may include logic to conduct a vertical blending weight determination based on horizontal pixel data associated with an image, and conduct a horizontal blending weight determination based on vertical pixel data associated with the image. Additionally, the logic may modify the image based on the vertical blending weight determination and the horizontal blending weight determination, wherein the vertical pixel data is excluded from the vertical blending weight determination, and the horizontal pixel data is excluded from the horizontal blending weight determination.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Alexey M. Supikov, Thomas R. Raoux
  • Publication number: 20140232742
    Abstract: Anti-aliasing methods and systems may include logic to conduct a vertical blending weight determination based on horizontal pixel data associated with an image, and conduct a horizontal blending weight determination based on vertical pixel data associated with the image. Additionally, the logic may modify the image based on the vertical blending weight determination and the horizontal blending weight determination, wherein the vertical pixel data is excluded from the vertical blending weight determination, and the horizontal pixel data is excluded from the horizontal blending weight determination.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 21, 2014
    Inventors: Alexander V Reshetov, Alexey M. Supikov, Thomas R. Raoux
  • Publication number: 20120268483
    Abstract: A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.
    Type: Application
    Filed: October 30, 2009
    Publication date: October 25, 2012
    Inventors: Alexei Soupikov, Maxim Y. Shevtsov, Alexander V. Reshetov
  • Patent number: 7990380
    Abstract: A given computer graphics scene may be rendered as a set of triangles. A set of photons may be distributed over the scene, and a number of steps may be performed for each triangle. For each triangle, a list of photons may be constructed. For that triangle, a set of control points may be identified for purposes of determining global illumination. For each control point, a specific illumination estimate may be computed. A kd-tree of the control points of the triangle may be built. An illumination estimate may then be drive for the triangle.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Igor Sevastianov, Alexei M. Soupikov, Alexander V. Reshetov
  • Patent number: 7969437
    Abstract: Embodiments of the invention provide for accelerated polygon intersection testing of rays against a set of polygons. The amount of computation required in the rendering process is reduced by preprocessing the scene into a data structure that can be more efficiently traversed. During the preprocessing stage, triangles such as triangle may be converted into vertex and edge representation.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin
  • Patent number: 7952574
    Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventor: Alexander V. Reshetov
  • Patent number: 7786991
    Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
  • Patent number: 7755628
    Abstract: A method, apparatus, and system related to thermal management. The method includes generating a beam including a group of rays; evaluating the beam against a spatially ordered geometrical database until the beam can no longer be evaluated as a whole in order to discard a portion of the spatially ordered geometrical database from further consideration; noting the location where the beam can no longer be evaluated as a whole; and traversing, starting at the noted location, the spatially ordered geometrical database for each of the rays by executing a query against the spatially ordered geometrical database not discarded by the evaluating.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, James T. Hurley
  • Publication number: 20080246763
    Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.
    Type: Application
    Filed: June 19, 2008
    Publication date: October 9, 2008
    Inventor: Alexander V. Reshetov
  • Patent number: 7414624
    Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventor: Alexander V. Reshetov
  • Publication number: 20080158227
    Abstract: A method, apparatus, and system related to thermal management. The method includes generating a beam including a group of rays; evaluating the beam against a spatially ordered geometrical database until the beam can no longer be evaluated as a whole in order to discard a portion of the spatially ordered geometrical database from further consideration; noting the location where the beam can no longer be evaluated as a whole; and traversing, starting at the noted location, the spatially ordered geometrical database for each of the rays by executing a query against the spatially ordered geometrical database not discarded by the evaluating.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Jim Hurley
  • Publication number: 20080150944
    Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.
    Type: Application
    Filed: March 4, 2008
    Publication date: June 26, 2008
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
  • Patent number: 7348975
    Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
  • Patent number: 7102636
    Abstract: Described are a novel graphical element known as a spatial patch and a system and method for rendering the spatial patch to create computer graphics. The spatial patch may include appearance data and displacement data for each of a plurality of nodes that together specify the color and geometry for typically a small portion of a surface of an object. The appearance and displacement data may be independent and irregular for each of the nodes in order to represent complexly colored and structured objects. The spatial patch may be processed independently and may have internal topology or structure to facilitate parallel processing. Accordingly, the spatial patch offers many quality and processing advantages over polygon mesh representations that have previously been used to create three-dimensional computer graphics.
    Type: Grant
    Filed: March 31, 2001
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Alexander V. Reshetov, Yevgeniy P. Kuzmin, Denis V. Ivanov, Alexander N. Yakovlev
  • Publication number: 20040203694
    Abstract: For a processor-based device capable of network communications, a workload associated with a wireless link to a network may be partitioned into software and hardware implementable portions based on a link communication profile. In response to a different link communication profile, the workload may be re-configured to simultaneously support another wireless link protocol different than that of the configured wireless link.
    Type: Application
    Filed: October 21, 2002
    Publication date: October 14, 2004
    Inventors: Samuel L.C. Wong, Ram C. Nalla, Alexander V. Reshetov, Alexei Soupikov, James T. Hurley
  • Publication number: 20030206184
    Abstract: A display device includes a controller and an interface to display content or media (e.g., image or video data) intended for one resolution into another resolution. The controller may associate a set of neighboring pixels with a target pixel within a first display content of a first resolution. Based on an indication derived from less than all of the neighboring pixels in the first display content of the first resolution, a second display content of a second resolution may be generated. The interface may be operably coupled to the controller to display the second display content of the second resolution. In one embodiment, a combination of neighboring pixels that reduces a cost function may be determined. Using a traveling salesman algorithm, an indication may be derived from pixel characteristics for a target pixel to reconstruct a first display content of a lower resolution into a second display content of a higher resolution by minimizing the cost function.
    Type: Application
    Filed: May 6, 2002
    Publication date: November 6, 2003
    Inventor: Alexander V. Reshetov
  • Publication number: 20020171644
    Abstract: Described are a novel graphical element known as a spatial patch and a system and method for rendering the spatial patch to create computer graphics. The spatial patch may include appearance data and displacement data for each of a plurality of nodes that together specify the color and geometry for typically a small portion of a surface of an object. The appearance and displacement data may be independent and irregular for each of the nodes in order to represent complexly colored and structured objects. The spatial patch may be processed independently and may have internal topology or structure to facilitate parallel processing. Accordingly, the spatial patch offers many quality and processing advantages over polygon mesh representations that have previously been used to create three-dimensional computer graphics.
    Type: Application
    Filed: March 31, 2001
    Publication date: November 21, 2002
    Inventors: Alexander V. Reshetov, Yevgeniy P. Kuzmin, Denis V. Ivanov, Alexander N. Yakovlev