Patents by Inventor Alexander V. Reshetov
Alexander V. Reshetov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10163187Abstract: A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.Type: GrantFiled: October 30, 2009Date of Patent: December 25, 2018Assignee: Intel CorproationInventors: Alexei Soupikov, Maxim Y. Shevtsov, Alexander V. Reshetov
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Patent number: 10121276Abstract: A method, computer readable medium, and system are disclosed for generating and utilizing infinite resolution texture acceleration data structures. The method for generating an infinite resolution texture acceleration data structure includes the steps of receiving an image; generating an infinite resolution texture acceleration data structure associated with the image that includes a texture map, a curve index map, and a curve data map; and storing the infinite resolution texture acceleration data structure in a memory. The texture map is a two-dimensional array of texels, each texel encoding a color value based on the image. The curve data map encodes parameters for at least one curve segment associated with the image. The curve index map associates each texel in the texture map with zero or more curve segments corresponding with the texel.Type: GrantFiled: December 1, 2016Date of Patent: November 6, 2018Assignee: NVIDIA CORPORATIONInventors: Alexander V. Reshetov, David Patrick Luebke
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Publication number: 20180158227Abstract: A method, computer readable medium, and system are disclosed for generating and utilizing infinite resolution texture acceleration data structures. The method for generating an infinite resolution texture acceleration data structure includes the steps of receiving an image; generating an infinite resolution texture acceleration data structure associated with the image that includes a texture map, a curve index map, and a curve data map; and storing the infinite resolution texture acceleration data structure in a memory. The texture map is a two-dimensional array of texels, each texel encoding a color value based on the image. The curve data map encodes parameters for at least one curve segment associated with the image. The curve index map associates each texel in the texture map with zero or more curve segments corresponding with the texel.Type: ApplicationFiled: December 1, 2016Publication date: June 7, 2018Inventors: Alexander V. Reshetov, David Patrick Luebke
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Patent number: 9582858Abstract: Anti-aliasing methods and systems may include logic to conduct a vertical blending weight determination based on horizontal pixel data associated with an image, and conduct a horizontal blending weight determination based on vertical pixel data associated with the image. Additionally, the logic may modify the image based on the vertical blending weight determination and the horizontal blending weight determination, wherein the vertical pixel data is excluded from the vertical blending weight determination, and the horizontal pixel data is excluded from the horizontal blending weight determination.Type: GrantFiled: May 2, 2012Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Alexander V. Reshetov, Alexey M. Supikov, Thomas R. Raoux
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Publication number: 20140232742Abstract: Anti-aliasing methods and systems may include logic to conduct a vertical blending weight determination based on horizontal pixel data associated with an image, and conduct a horizontal blending weight determination based on vertical pixel data associated with the image. Additionally, the logic may modify the image based on the vertical blending weight determination and the horizontal blending weight determination, wherein the vertical pixel data is excluded from the vertical blending weight determination, and the horizontal pixel data is excluded from the horizontal blending weight determination.Type: ApplicationFiled: May 2, 2012Publication date: August 21, 2014Inventors: Alexander V Reshetov, Alexey M. Supikov, Thomas R. Raoux
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Publication number: 20120268483Abstract: A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.Type: ApplicationFiled: October 30, 2009Publication date: October 25, 2012Inventors: Alexei Soupikov, Maxim Y. Shevtsov, Alexander V. Reshetov
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Patent number: 7990380Abstract: A given computer graphics scene may be rendered as a set of triangles. A set of photons may be distributed over the scene, and a number of steps may be performed for each triangle. For each triangle, a list of photons may be constructed. For that triangle, a set of control points may be identified for purposes of determining global illumination. For each control point, a specific illumination estimate may be computed. A kd-tree of the control points of the triangle may be built. An illumination estimate may then be drive for the triangle.Type: GrantFiled: September 30, 2004Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Igor Sevastianov, Alexei M. Soupikov, Alexander V. Reshetov
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Patent number: 7969437Abstract: Embodiments of the invention provide for accelerated polygon intersection testing of rays against a set of polygons. The amount of computation required in the rendering process is reduced by preprocessing the scene into a data structure that can be more efficiently traversed. During the preprocessing stage, triangles such as triangle may be converted into vertex and edge representation.Type: GrantFiled: December 28, 2004Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin
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Patent number: 7952574Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.Type: GrantFiled: June 19, 2008Date of Patent: May 31, 2011Assignee: Intel CorporationInventor: Alexander V. Reshetov
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Patent number: 7786991Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.Type: GrantFiled: March 4, 2008Date of Patent: August 31, 2010Assignee: Intel CorporationInventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
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Patent number: 7755628Abstract: A method, apparatus, and system related to thermal management. The method includes generating a beam including a group of rays; evaluating the beam against a spatially ordered geometrical database until the beam can no longer be evaluated as a whole in order to discard a portion of the spatially ordered geometrical database from further consideration; noting the location where the beam can no longer be evaluated as a whole; and traversing, starting at the noted location, the spatially ordered geometrical database for each of the rays by executing a query against the spatially ordered geometrical database not discarded by the evaluating.Type: GrantFiled: December 29, 2006Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: Alexander V. Reshetov, Alexei M. Soupikov, James T. Hurley
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Publication number: 20080246763Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.Type: ApplicationFiled: June 19, 2008Publication date: October 9, 2008Inventor: Alexander V. Reshetov
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Patent number: 7414624Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.Type: GrantFiled: October 28, 2005Date of Patent: August 19, 2008Assignee: Intel CorporationInventor: Alexander V. Reshetov
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Publication number: 20080158227Abstract: A method, apparatus, and system related to thermal management. The method includes generating a beam including a group of rays; evaluating the beam against a spatially ordered geometrical database until the beam can no longer be evaluated as a whole in order to discard a portion of the spatially ordered geometrical database from further consideration; noting the location where the beam can no longer be evaluated as a whole; and traversing, starting at the noted location, the spatially ordered geometrical database for each of the rays by executing a query against the spatially ordered geometrical database not discarded by the evaluating.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Jim Hurley
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Publication number: 20080150944Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.Type: ApplicationFiled: March 4, 2008Publication date: June 26, 2008Inventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
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Patent number: 7348975Abstract: Embodiments provide for ray tracing traversal that relies on selected geometrical properties of the application to reduce the number of operations required during each traversal step. The traversal algorithm does not depend on the number of rays in the group. As a result, multi-level traversal schemes may be implemented, starting with a large number of rays in a group and then reducing it as needed to maintain group coherency. Multi-level traversal schemes may be created by splitting large groups of rays while traversing acceleration structures.Type: GrantFiled: December 28, 2004Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Alexander V. Reshetov, Alexei M. Soupikov, Alexander D. Kapustin, James T. Hurley
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Patent number: 7102636Abstract: Described are a novel graphical element known as a spatial patch and a system and method for rendering the spatial patch to create computer graphics. The spatial patch may include appearance data and displacement data for each of a plurality of nodes that together specify the color and geometry for typically a small portion of a surface of an object. The appearance and displacement data may be independent and irregular for each of the nodes in order to represent complexly colored and structured objects. The spatial patch may be processed independently and may have internal topology or structure to facilitate parallel processing. Accordingly, the spatial patch offers many quality and processing advantages over polygon mesh representations that have previously been used to create three-dimensional computer graphics.Type: GrantFiled: March 31, 2001Date of Patent: September 5, 2006Assignee: Intel CorporationInventors: Alexander V. Reshetov, Yevgeniy P. Kuzmin, Denis V. Ivanov, Alexander N. Yakovlev
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Publication number: 20040203694Abstract: For a processor-based device capable of network communications, a workload associated with a wireless link to a network may be partitioned into software and hardware implementable portions based on a link communication profile. In response to a different link communication profile, the workload may be re-configured to simultaneously support another wireless link protocol different than that of the configured wireless link.Type: ApplicationFiled: October 21, 2002Publication date: October 14, 2004Inventors: Samuel L.C. Wong, Ram C. Nalla, Alexander V. Reshetov, Alexei Soupikov, James T. Hurley
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Publication number: 20030206184Abstract: A display device includes a controller and an interface to display content or media (e.g., image or video data) intended for one resolution into another resolution. The controller may associate a set of neighboring pixels with a target pixel within a first display content of a first resolution. Based on an indication derived from less than all of the neighboring pixels in the first display content of the first resolution, a second display content of a second resolution may be generated. The interface may be operably coupled to the controller to display the second display content of the second resolution. In one embodiment, a combination of neighboring pixels that reduces a cost function may be determined. Using a traveling salesman algorithm, an indication may be derived from pixel characteristics for a target pixel to reconstruct a first display content of a lower resolution into a second display content of a higher resolution by minimizing the cost function.Type: ApplicationFiled: May 6, 2002Publication date: November 6, 2003Inventor: Alexander V. Reshetov
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Publication number: 20020171644Abstract: Described are a novel graphical element known as a spatial patch and a system and method for rendering the spatial patch to create computer graphics. The spatial patch may include appearance data and displacement data for each of a plurality of nodes that together specify the color and geometry for typically a small portion of a surface of an object. The appearance and displacement data may be independent and irregular for each of the nodes in order to represent complexly colored and structured objects. The spatial patch may be processed independently and may have internal topology or structure to facilitate parallel processing. Accordingly, the spatial patch offers many quality and processing advantages over polygon mesh representations that have previously been used to create three-dimensional computer graphics.Type: ApplicationFiled: March 31, 2001Publication date: November 21, 2002Inventors: Alexander V. Reshetov, Yevgeniy P. Kuzmin, Denis V. Ivanov, Alexander N. Yakovlev