Patents by Inventor Alexander Vasilevskiy

Alexander Vasilevskiy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210208959
    Abstract: Receive, by a central controller engine, a user request to perform one or more operations associated with user data, wherein the user data includes first data and second data. Select, by the central controller engine based on the user request, a first service provider interface (SPI) integrated into a first service, the first SPI being configured to operate on the first data in a first datastore associated with the first service. The first SPI including a first service interface component configured based on a uniform access specification. Obtain, by the first SPI, the first data, the first data being formatted according to a first service data specification. Transform, by the first SPI based on the uniform access specification, the first data, thereby generating transformed first data formatted according to the uniform access specification. Provide, by the first SPI, the transformed first data to a target service.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Applicant: Zuora, Inc.
    Inventors: Henning Schmiedehausen, Nicolas Fusseder, Alexander Vasilevskiy
  • Publication number: 20200379829
    Abstract: A multi-tenant system comprises a monolithic database storing global records, each including global fields common for all tenants; a custom field database storing custom records, each including custom fields for a tenant; a custom field record service processing a custom record storage request by instructing the custom field database to store custom field values of the custom record for the tenant, and processing a custom record fetch request by instructing the custom field database to retrieve the custom field values; a monolithic application configured to receive a record storage or fetch request, configured to partition the record storage request into the global record storage request and the custom record storage request, configured to send the custom record storage request to the custom field record service, configured to partition the record fetch request into the global record fetch request and the custom record fetch request, and configured to send the custom record fetch request to the custom field r
    Type: Application
    Filed: June 3, 2020
    Publication date: December 3, 2020
    Applicant: Zuora, Inc.
    Inventors: Alexander Vasilevskiy, Henning Schmiedehausen, Suryatej Mukkamalla, Rui Zhang
  • Publication number: 20200379970
    Abstract: A multi-tenant system, comprises a main storage system including: a monolithic database storing global records associated with global objects, each global object including global fields common for all tenants; a monolithic application configured to process a particular global record storage request by instructing the monolithic database to store particular global field values of the particular global record for a particular tenant, and to process a particular global record fetch request by instructing the monolithic database to retrieve the one or more particular global field values; a custom object storage system including: a custom object database configured to store custom records associated with one or more custom objects, each custom object including one or more custom fields for a tenant; a custom object record service configured to process a particular custom record storage request by instructing the custom object database to store one or more particular custom field values for the tenant, and to proce
    Type: Application
    Filed: June 3, 2020
    Publication date: December 3, 2020
    Applicant: Zuora, Inc.
    Inventors: Alexander Vasilevskiy, Henning Schmiedehausen, Chi Lap Hoang, Rodolfo Gentini Fernandez, Suryatej Mukkamalla
  • Publication number: 20190370258
    Abstract: Receive, by an arbitrary query user interface, a user request to perform a query associated with user data, wherein the user data includes first data and second data. Partition, by a coordinator node of an arbitrary query engine, the query into at least a first sub-query and a second sub-query. Assign, by the coordinator node of the arbitrary query engine, the first sub-query to a first query node of the arbitrary query engine.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 5, 2019
    Applicant: Zuora, Inc.
    Inventors: Henning Schmiedehausen, Alexander Vasilevskiy
  • Patent number: 9268540
    Abstract: Embodiments relate to generating short displacement instructions. An aspect includes performing code generation by a compiler to generate an instructions. Another aspect includes determining whether the generated instruction supports long displacement. Another aspect includes based on a determination that the generated instruction does not support long displacement, determining whether a short displacement budget is full. Another aspect includes based on a determination that the short displacement budget is not full, marking data associated with the instruction in a symbol table maintained by the compiler. Another aspect includes incrementing the short displacement budget using a size of the marked data associated with the instruction. Another aspect includes based on a determination that the short displacement budget is full, performing a low cost fix up.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: February 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ye Tian, Alexander Vasilevskiy
  • Patent number: 9146740
    Abstract: Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran Siu, Timothy J. Slegel, Alexander Vasilevskiy
  • Patent number: 9146739
    Abstract: Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran Siu, Timothy J. Slegel, Alexander Vasilevskiy
  • Publication number: 20140123102
    Abstract: Embodiments relate to generating short displacement instructions. An aspect includes performing code generation by a compiler to generate an instructions. Another aspect includes determining whether the generated instruction supports long displacement. Another aspect includes based on a determination that the generated instruction does not support long displacement, determining whether a short displacement budget is full. Another aspect includes based on a determination that the short displacement budget is not full, marking data associated with the instruction in a symbol table maintained by the compiler. Another aspect includes incrementing the short displacement budget using a size of the marked data associated with the instruction. Another aspect includes based on a determination that the short displacement budget is full, performing a low cost fix up.
    Type: Application
    Filed: October 16, 2013
    Publication date: May 1, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ye Tian, Alexander Vasilevskiy
  • Publication number: 20130339697
    Abstract: Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field.
    Type: Application
    Filed: March 5, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran Siu, Timothy J. Slegel, Alexander Vasilevskiy
  • Publication number: 20130339691
    Abstract: Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran Siu, Timothy J. Slegel, Alexander Vasilevskiy
  • Patent number: 8250557
    Abstract: There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to obtain a ranking of nodes in the DDG after setting delays at all identified by-pass pairs of nodes in the DDG to 0. From among a list of identified by-pass pairs of nodes, a node that is identified as being the least important to schedule early is marked as “bonded” to its successor, and the corresponding delay for that identified node is set to 0. Node rankings are re-computed and the bonded by-pass pair of nodes are scheduled in consecutive execution cycles with a delay of 0 to increase the likelihood that a by-pass can be successfully taken during run-time execution.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Alexander Vasilevskiy
  • Patent number: 8042100
    Abstract: Systems, methods, and computer products for evaluating robustness of a list scheduling framework. Exemplary embodiments include a method for evaluating the robustness of a list scheduling framework, the method including identifying a set of compiler benchmarks known to be sensitive to an instruction scheduler, running the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, running the set of benchmarks against a plurality of random heuristics Hrand[G]i, and collect a plurality of respective execution times Exec(Hrand[G])i, computing a robustness of the list scheduling framework, and checking robustness check it against a pre-determined threshold.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Joran S. C. Siu, Alexander Vasilevskiy
  • Patent number: 7908596
    Abstract: Automatic inspection of compiled code. In response to revising a compiler, the functionality of that compiler is verified. Specific code is compiled using a first version of the compiler, as well as a second version of the compiler. Each compiled code is then applied to machine state to obtain multiple machine states. The machine states are then compared to determine if they are equal.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Alexander Vasilevskiy
  • Patent number: 7770161
    Abstract: A computer implemented method, system, and computer usable program code for selective instruction scheduling. A determination is made whether a region of code exceeds a modification threshold after performing register allocation on the region of code. The region of code is marked as a modified region of code in response to the determination that the region of code exceeds the modification threshold. A determination is made whether the region of code exceeds an execution threshold in response to the determination that the region of code is marked as a modified region of code. Post-register allocation instruction scheduling is performed on the region of code in response to the determination that the region of code is marked as a modified region of code and the determination that the region of code exceeds the execution threshold.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Marcel M. Mitran, Alexander A. Vasilevskiy
  • Publication number: 20090064109
    Abstract: Systems, methods, and computer products for evaluating robustness of a list scheduling framework. Exemplary embodiments include a method for evaluating the robustness of a list scheduling framework, the method including identifying a set of compiler benchmarks known to be sensitive to an instruction scheduler, running the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, running the set of benchmarks against a plurality of random heuristics Hrand[G]i, and collect a plurality of respective execution times Exec(Hrand[G])i, computing a robustness of the list scheduling framework, and checking robustness check it against a pre-determined threshold.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marcel Mitran, Joran S.C. Siu, Alexander Vasilevskiy
  • Publication number: 20090055628
    Abstract: Assigning each of a plurality of memory fetch units to any of a plurality of candidate variables to reduce load-hit-store delays, wherein a total number of required memory fetch units is minimized. A plurality of store/load pairs are identified. A dependency graph is generated by creating a node Nx for each store to variable X and a node Ny for each load of variable Y and, unless X=Y, for each store/load pair, creating an edge between a respective node Nx and a corresponding node Ny; for each created edge, labeling the edge with a heuristic weight; labeling each node Nx with a node weight Wx that combines a plurality of respective edge weights of a plurality of corresponding nodes Nx such that Wx=??xj; and determining a color for each of the graph nodes using k distinct colors wherein k is minimized such that no adjacent nodes joined by an edge between a respective node Nx and a corresponding node Ny have an identical color; and assigning a memory fetch unit to each of the k distinct colors.
    Type: Application
    Filed: August 21, 2007
    Publication date: February 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINE CORPORATION
    Inventors: Marcel Mitran, Joran S.C. Siu, Alexander Vasilevskiy
  • Publication number: 20080216062
    Abstract: There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to obtain a ranking of nodes in the DDG after setting delays at all identified by-pass pairs of nodes in the DDG to 0. From among a list of identified by-pass pairs of nodes, a node that is identified as being the least important to schedule early is marked as “bonded” to its successor, and the corresponding delay for that identified node is set to 0. Node rankings are re-computed and the bonded by-pass pair of nodes are scheduled in consecutive execution cycles with a delay of 0 to increase the likelihood that a by-pass can be successfully taken during run-time execution.
    Type: Application
    Filed: May 7, 2008
    Publication date: September 4, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Vasilevskiy, Marcel Mitran
  • Publication number: 20080168426
    Abstract: Automatic inspection of compiled code. In response to revising a compiler, the functionality of that compiler is verified. Specific code is compiled using a first version of the compiler, as well as a second version of the compiler. Each compiled code is then applied to machine state to obtain multiple machine states. The machine states are then compared to determine if they are equal.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marcel Mitran, Alexander Vasilevskiy
  • Patent number: 7392516
    Abstract: There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to obtain a ranking of nodes in the DDG after setting delays at all identified by-pass pairs of nodes in the DDG to 0. From among a list of identified by-pass pairs of nodes, a node that is identified as being the least important to schedule early is marked as “bonded” to its successor, and the corresponding delay for that identified node is set to 0. Node rankings are re-computed and the bonded by-pass pair of nodes are scheduled in consecutive execution cycles with a delay of 0 to increase the likelihood that a by-pass can be successfully taken during run-time execution.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alexander Vasilevskiy, Marcel Mitran
  • Publication number: 20070150880
    Abstract: A computer implemented method, system, and computer usable program code for selective instruction scheduling. A determination is made whether a region of code exceeds a modification threshold after performing register allocation on the region of code. The region of code is marked as a modified region of code in response to the determination that the region of code exceeds the modification threshold. A determination is made whether the region of code exceeds an execution threshold in response to the determination that the region of code is marked as a modified region of code. Post-register allocation instruction scheduling is performed on the region of code in response to the determination that the region of code is marked as a modified region of code and the determination that the region of code exceeds the execution threshold.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Marcel Mitran, Alexander Vasilevskiy