Patents by Inventor Alexander Von Glasow
Alexander Von Glasow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150228436Abstract: A fuse may be provided, which may include: a first fuse link; a second fuse link coupled in series to the first fuse link; and a connection element coupled between the first and second fuse links and disposed in the same level as the first and second fuse links.Type: ApplicationFiled: January 30, 2015Publication date: August 13, 2015Inventors: Franz Ungar, Gunther Lehmann, Armin Fischer, Alexander Von Glasow, Sascha Siegler
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Patent number: 8569820Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: GrantFiled: January 6, 2012Date of Patent: October 29, 2013Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Patent number: 8487453Abstract: A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip.Type: GrantFiled: February 22, 2011Date of Patent: July 16, 2013Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow
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Patent number: 8323991Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.Type: GrantFiled: December 29, 2010Date of Patent: December 4, 2012Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow, Jochen Von Hagen
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Patent number: 8211720Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.Type: GrantFiled: December 29, 2010Date of Patent: July 3, 2012Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow, Jochen Von Hagen
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Publication number: 20120099243Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: ApplicationFiled: January 6, 2012Publication date: April 26, 2012Applicant: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Patent number: 8138539Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: GrantFiled: November 29, 2007Date of Patent: March 20, 2012Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Publication number: 20110140236Abstract: A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Inventors: Armin Fischer, Alexander Von Glasow
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Publication number: 20110097826Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.Type: ApplicationFiled: December 29, 2010Publication date: April 28, 2011Applicant: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow, Jochen von Hagen
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Patent number: 7919363Abstract: A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip.Type: GrantFiled: April 21, 2006Date of Patent: April 5, 2011Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow
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Patent number: 7888672Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.Type: GrantFiled: May 19, 2005Date of Patent: February 15, 2011Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander von Glasow, Jochen von Hagen
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Patent number: 7777300Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.Type: GrantFiled: September 18, 2007Date of Patent: August 17, 2010Assignee: Infineon Technologies AGInventors: Helmut Tews, Hans-Gerd Jetten, Alexander von Glasow, Hans-Joachim Barth
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Publication number: 20090141424Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
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Publication number: 20090073633Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Helmut Tews, Hans-Gerd Jetten, Alexander Von Glasow, Hans-Joachim Barth
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Patent number: 7327152Abstract: An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection unit, an integrated supply unit, and a control unit. The integrated detection unit detects at least one physical property for each of the test structures. The integrated supply unit supplies each of the test structures with a current or a voltage in switchable fashion independently of one another. The control unit is connected to outputs of the detection unit on an input side and controls the supply unit dependent on the detection results.Type: GrantFiled: September 19, 2003Date of Patent: February 5, 2008Assignee: Infineon Technologies, AGInventors: Armin Fischer, Alexander von Glasow
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Patent number: 7315998Abstract: An integrated circuit arrangement having a metallization layer, an interconnect dielectric, electrically conductive interconnect intermediate material, electrically conductive connecting sections, connecting section dielectric between the connecting sections, and connecting section intermediate material. The metallization layer contains electrically conductive interconnects between which the interconnect dielectric is disposed. The electrically conductive interconnect intermediate material is arranged between a side area of an interconnect and the interconnect dielectric. The electrically conductive connecting sections in each case form a section of an electrically conductive connection to or from an interconnect and the connecting section dielectric is between the connecting sections. The connecting section intermediate material is arranged in each case between a connecting section and the connecting section dielectric and/or between a connecting section and an interconnect.Type: GrantFiled: August 14, 2003Date of Patent: January 1, 2008Assignee: Infineon Technologies AGInventors: Armin Fischer, Alexander Von Glasow
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Publication number: 20050275103Abstract: An integrated circuit arrangement having a metallization layer, an interconnect dielectric, electrically conductive interconnect intermediate material electrically conductive connecting sections, connecting section dielectric between the connecting sections and connecting section intermediate material. The metallization layer contains electrically conductive interconnects between which the interconnect dielectric is disposed. The electrically conductive interconnect intermediate material is arranged between a side area of an interconnect and the interconnect dielectric. The electrically conductive connecting sections in each case form a section of an electrically conductive connection to or from an interconnect and the connecting section dielectric is between the connecting sections. The connecting section intermediate material is arranged in each case between a connecting section and the connecting section dielectric and/or between a connecting section and an interconnect.Type: ApplicationFiled: September 14, 2003Publication date: December 15, 2005Inventors: Armin Fischer, Alexander Von Glasow
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Publication number: 20050211980Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.Type: ApplicationFiled: May 19, 2005Publication date: September 29, 2005Inventors: Armin Fischer, Alexander von Glasow, Jochen von Hagen
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Patent number: 6940720Abstract: An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.Type: GrantFiled: April 25, 2003Date of Patent: September 6, 2005Assignee: Infineon Technologies AGInventors: Armin Fischer, Johann Helneder, Heinrich Körner, Markus Schwerd, Wolfgang Walter, Alexander Von Glasow
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Publication number: 20040011510Abstract: An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.Type: ApplicationFiled: April 25, 2003Publication date: January 22, 2004Inventors: Armin Fischer, Johann Helneder, Heinrich Korner, Markus Schwerd, Wolfgang Walter, Alexander Von Glasow