Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Abstract: Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.

Abstract: A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

Abstract: A large block synthesis (LBS) process pre-optimizes selected submacros by synthesizing the submacros using timing assertions and placement abstracts, removing placement information, and assigning weights to the internal nets of the submacros that are much higher than weights used for external (e.g., top-level) nets. The timing assertions include an input arrival time, a required output arrival time, and an output pin capacitance loading for the logic block, and the placement abstract is generated by condensing input and output pins of the logic block at a center of gravity of the logic block. The submacros to be pre-optimized can automatically be identified using an attribute to indicate pre-optimization, or by determining that the submacro is one of many instances in the design. The higher weights for the submacro nets define soft-bounds for the logic which still allow relocation of submacro components. The pre-optimization results in significantly reduced synthesis runtime.

Abstract: Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiation

Abstract: A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

Abstract: A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Abstract: Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiation

Abstract: Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization.

Abstract: A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.

Abstract: A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of (a) identifying corresponding top-sheets of the first hierarchy level in the design versions; (b) generating a list of all sub-sheets for each top-sheet and comparing the lists to identify added, removed and common sheets of the corresponding top-sheets; (c) defining the common sheets as corresponding top-sheets of a next hierarchy level; and (d) repeating steps (a)-(c) until at least one of the top-sheets does not comprise any sub-sheet.

Abstract: The present invention relates to creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by tightly coupling placement and routing. An initial placement of shapes of extended size is succeeded by a routing step that tries to create wires between shapes of reduced size. If that fails, it is tried to wire shapes of extended size instead. The wiring can be combined with a delta-placement of shapes within shapes of extended size such that wires connected to shapes of extended size also connect to the shapes.

Abstract: According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

Abstract: A method for comparing two designs of electronic circuits, especially for comparing different versions of a design for an electronic circuit, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of: a) analyzing the hierarchies of said design versions to identify added, removed and common sheets; b) determining differences between common sheets to identify modified sheets; and c) visualizing the combined hierarchies of said design versions wherein added, removed and modified sheets are marked.

Abstract: According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

Abstract: The present invention relates to a method, a tool, and a computer program product for creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by tightly coupling placement and routing. An initial placement of shapes of extended size is succeeded by a routing step that tries to create wires between shapes of reduced size. If that fails, it is tried to wire shapes of extended size instead. The wiring can be combined with a delta-placement of shapes within shapes of extended size such that wires connected to shapes of extended size also connect to the shapes.